LT4295 datasheet(30/50 Pages) AD

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LTC9101-1/

LTC9102/LTC9103

Rev. 0

For more information www.analog.com

APPLICATIONS INFORMATION

Any individual class signature that exceeds the class cur-

rent limit is flagged as an invalid classification result. Any

sequence of class signatures that does not represent a

legal sequence based on PD configuration will likewise

be flagged as an invalid classification result.

Auto Mode Maximum PSE Power

In auto mode the LTC9101-1/LTC9102/LTC9103 auto-

matically detects, classifies and powers all connected

valid PDs. In order to do this, each port must be config-

ured for its maximum power allocation. Select the resistor

RPWRMD from Table 12 that reflects each port’s maximum

power delivery capability.

Connect the PWRMD0 pin of the LTC9102/LTC9103 at ID

address 00b to VEE through RPWRMD. The PWRMD0 pin

of the LTC9102/LTC9103 at ID address 01b, 10b, and 11b

must be left floating. The PWRMD1 pin of each LTC9102/

LTC9103 must be left floating. The PWRMD resistor is

measured at reset.

The maximum power allocation is a reflection of the power

supply and power path capability. The PWRMD resistor

setting is applied to every port in this chipset, across all

quads and ICs. Accordingly, the PWRMD resistor must be

set with consideration for each port’s power path capabil-

ity and for the system’s power supply capability.

When AUTO is low the PWRMD0 pin setting is ignored.

Table 12. Auto Mode Maximum Delivered Power Capabilities

RPWRMD

2-PAIR MODE

4-PAIR MODE

MAX PORT

POWER

MAX PORT POWER

SINGLE-SIGNATURE PD

MAX PORT POWER

DUAL-SIGNATURE PD*

Open

Class 3: 13.0W

24.3k

Class 4: 25.5W

18.7k

Class 4: 25.5W

14.3k

Class 5: 40.0W

Class 3: 13.0W

11.0k

Class 6: 51.0W

Class 4: 25.5W

8.45k

Class 7: 62.0W

Class 4: 25.5W

6.49k

Class 8: 71.3W

Class 5: 40.0W

*In auto mode, total port power allocation is double this value, reflecting

the two halves of a dual-signature PD.

Class Reset

An issue arises when a Class 4 or Class 5 dual-signature

PD is connected. In order to determine PD Type, three

class events are issued. Based on the class event count,

the PD has been allocated 25.5W. If the PSE desires to

both determine PD Type (3 events) and demote to 13W

(1 event), a class reset event must be issued as shown

in Figure 22.

Figure 22.

9101123 F22

VCLASSMIN

VMARKMAX

VRESET

DETECT

1ST

CLASS

1ST

MARK

1ST

MARK

2ND

MARK

2ND

CLASS

3RD

CLASS

1ST

CLASS

POWER ON

CLASS

RESET

Class Reset Event Between Class Sequences

A class reset event is issued by maintaining the channel

voltage below 2.8V for at least tCLASS_RESET. The subse-

quent single event classification is used to demote the

PD to 13W.

In auto mode the 4PID information and the state of

4PVALID are used to automatically determine the number

of powered channels.

LLDP signaling may, at some time later, determine the

pre-bt PD is actually four pair capable and the LTC9101-1/

LTC9102/LTC9103 may be instructed to deliver 4-pair

power.

Invalid Multi-Event Classification Combinations

The 802.3bt specification defines a set of valid class sig-

nature combinations. All PDs return the same classifica-

tion signature on the first two class events. Type 3 and 4

PDs modify the classification signature on all subsequent

class events. For example, a single-signature Class 5 PD

will respond to the class events 1, 2, 3, and 4 with a class

signature of 4, 4, 0, and 0, respectively.

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