LT4295 datasheet(38/50 Pages) AD

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LTC9101-1/

LTC9102/LTC9103

Rev. 0

For more information www.analog.com

APPLICATIONS INFORMATION

ISOLATION REQUIREMENTS

IEEE 802.3 Ethernet specifications require that network

segments (including PoE circuitry) be electrically isolated

from the chassis ground of each network interface device.

However, network segments are not required to be iso-

lated from each other, provided that the segments are

connected to devices residing within a single building on

a single power distribution system.

If the PSE is part of a larger system, contains additional

external non-Ethernet ports, or must be referenced to pro-

tective ground for some other reason, the PoE subsystem

must be electrically isolated from the rest of the system.

The LTC9101-1/LTC9102/LTC9103 chipset simplifies PSE

isolation by allowing the LTC9101-1 chip to reside on the

non-isolated side. There it can receive power from the

main logic supply and connect directly to the I2C/SMBus

bus. In this case, the SDAIN and SDAOUT pins can be tied

together and will act as a standard I2C/SMBus SDA pin.

Isolation between the LTC9101-1 and LTC9102/LTC9103

is implemented using a proprietary transformer-based

communication protocol. Additional details are provided

in the High-Speed Data Isolation section of this data sheet.

For simple devices, such as unmanaged PoE switches,

the isolation requirement can be met by using an isolated

main power supply for the entire device. This strategy can

be used if the device has no electrically conducting ports

other than twisted-pair Ethernet. The LTC9101-1 may

directly connect to the LTC9102s/LTC9103s in the above

circumstances, or if the system already provides isolation.

EXTERNAL COMPONENT SELECTION

Power Supplies

The LTC9101-1/LTC9102/LTC9103 requires two supply

voltages to operate. VDD requires 3.3V (nominally) relative

to DGND. VEE requires a negative voltage of between –51V

to –57V for Type 2 and 3 PSEs, or –53V to –57V for Type

4 PSEs, relative to AGND.

Bus Addressing

The LTC9101-1’s primary 7-bit serial bus address is

010A3A200b, with bits 3:2 set by AD3:AD2 respectively. In

Figure 6 through Figure 9, AD3:AD2 are set by LTC9101-1

pins and AD1:AD0 are inferred by device configuration.

See Table 4 for device configuration options. Depending on

device configuration, up to 12 I2C addresses will be popu-

lated from the I2C base address upwards. All LTC9101-1s

also respond to the broadcast address 0110000b, allow-

ing the host to write the same command (typically con-

figuration commands) to multiple LTC9101-1s in a single

transaction. If the LTC9101-1 is asserting INT, it will also

respond to the alert response address (0001100b) per the

SMBus specification.

Each LTC9101-1/LTC9102/LTC9103 is logically com-

posed of multiple four port groups, known as quads, each

packed into a single I2C address. See Device Configuration

section for details. For example, if CFG[2:0] is set to 000,

an LTC9101-1 is configured as an 8-port or 12-port device

when attached to an LTC9102 or an LTC9103, respectively

(see Table 4). This configuration requires two or three

consecutive I2C addresses, with quad offset 0 starting at

the I2C base address.

Note that any individual quad I2C address greater than or

equal to 0x30 (the broadcast address) will be automati-

cally disabled.

Interrupts and SMBAlert

Most port events can be configured to trigger an inter-

rupt, asserting INT and alerting the host to the event. This

removes the need for the host to poll the LTC9101-1,

minimizing serial bus traffic and conserving host CPU

cycles. Multiple LTC9101-1s can share a common INT

line, with the host using the SMBAlert protocol (ARA) to

determine which LTC9101-1 caused an interrupt.

For information on serial bus usage and device configura-

tion and status, refer to the LTC9101-1 Software Interface

guide. Contact Analog Devices to request this document.

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