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MAX5652 Datasheet(PDF) 3 Page - Maxim Integrated Products |
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MAX5652 Datasheet(HTML) 3 Page - Maxim Integrated Products |
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3 / 14 page ![]() 16-Bit, Parallel-Input, Voltage-Output DACs with Internal Reference _______________________________________________________________________________________ 3 ELECTRICAL CHARACTERISTICS—MAX5650 (continued) (AVDD = DVDD = +4.75V to +5.25V, AGND = DGND = GND = 0V, VREF = internal, RL = ∞, CL = 10pF, CREF = 1µF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DYNAMIC PERFORMANCE—ANALOG SECTION Output Settling Time 7F60H to 80A0H or 80A0H to 7F60H to 0.5 LSB2 µs DAC Glitch Impulse Major carry transition 10 nV·s Digital Feedthrough Code = 0000 hex; CSLSB = CSMSB = DVDD, D0–D15 transition from 0 to DVDD 3 nV·s DYNAMIC PERFORMANCE—VOLTAGE REFERENCE SECTION Frequency = 0.1Hz to 10Hz 15 µVP-P Noise Voltage (Note 6) Frequency = 10Hz to 1kHz 12 µVRMS VREF Glitch Impulse For zero-scale to full-scale or full-scale to zero-scale transition 10 nV·s STATIC PERFORMANCE—DIGITAL INPUTS Input High Voltage VIH (Note 8) 2.4 V Input Low Voltage VIL (Note 8) 0.8 V Input Current IIN ±1 µA Input Capacitance CIN 5pF POWER SUPPLY Analog Supply Range AVDD 4.75 5.25 V Digital Supply Range DVDD (Note 9) AVDD - 0.3 AVDD + 0.3 V Positive Supply Current IAVDD + IDVDD All digital inputs at DVDD or 0V, AVDD = DVDD 2mA TIMING CHARACTERISTICS (Figure 4) CSMSB and CSLSB Pulse Width tCS 40 ns WR Pulse Width tWR 40 ns CSMSB or CSLSB to WR Setup Time tCWS 0ns CSMSB or CSLSB to WR Hold Time tCWH 0ns Data Valid to WR Setup Time tDWS 40 ns Data Valid to WR Hold Time tDWH 0ns LDAC Pulse Width tLDAC 40 ns CLR Pulse Width tCLR 40 ns Note 1: 100% production tested at TA = +25°C and TA = +85°C. Guaranteed by design at TA = -40°C. Note 2: Temperature coefficient is determined by the box method in which the maximum change over the temperature range is divided by ∆T. Note 3: Gain error is measured at the full-scale code and is calculated with respect to the reference voltage (REF). Note 4: Resistor tolerance is typically ±20%. Note 5: Guaranteed by design, not production tested. Note 6: Noise is measured at the reference output. Note 7: Min/max range guaranteed by gain-error test. Operation outside min/max limits results in degraded performance. Note 8: The devices draw higher supply current when the digital inputs are driven between (DVDD - 0.5V) and (DGND + 0.5V). See Digital Supply Current vs. Digital Input Voltage in the Typical Operating Characteristics. Note 9: For optimal performance AVDD = DVDD. |
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