| Electronic Components Datasheet Search |
|
MAX5652 Datasheet(PDF) 6 Page - Maxim Integrated Products |
|
|
|||||||||||||||||||||||||||||
MAX5652 Datasheet(HTML) 6 Page - Maxim Integrated Products |
|
6 / 14 page ![]() 16-Bit, Parallel-Input, Voltage-Output DACs with Internal Reference 6 _______________________________________________________________________________________ Pin Description PIN NAME FUNCTION 1 D0 Data Input Bit 0 (LSB) 2 D1 Data Input Bit 1 3 D2 Data Input Bit 2 4 D3 Data Input Bit 3 5 D4 Data Input Bit 4 6 D5 Data Input Bit 5 7 D6 Data Input Bit 6 8 D7 Data Input Bit 7 9 D8 Data Input Bit 8 10 D9 Data Input Bit 9 11 D10 Data Input Bit 10 12 D11 Data Input Bit 11 13 D12 Data Input Bit 12 14 D13 Data Input Bit 13 15 D14 Data Input Bit 14 16 D15 Data Input Bit 15 (MSB) 17 DGND Digital Ground 18 DVDD Digital Supply. Bypass DVDD to DGND with a 0.1µF capacitor as close to the device as possible. 19 CSLSB Lower 8-Bit Active-Low Chip Select. When CSLSB is driven low the data inputs D0–D7 are loaded to the input and DAC registers depending on the state of WR and LDAC (see Table 1). 20 CSMSB Upper 8-Bit Active-Low Chip Select. When CSMSB is driven low the data inputs D8–D15 are loaded to the input and DAC registers depending on the state of WR and LDAC (see Table 1). 21 WR Active-Low Write Input. While chip select ( CSLSB and/or CSMSB) is low, the data on D0–D7 and/or D8–D15 is presented to the input register when WR is low. A rising edge on WR then latches the data to the input register (see Table 1). Hold WR low to make the input register transparent. 22 LDAC Asynchronous Active-Low Load DAC Input. When LDAC is low, the data in the input register is presented to the DAC register. A rising edge on LDAC then latches the data to the DAC register (see Table 1). Hold WR and LDAC low to perform a write-through operation. 23 CLR Asynchronous Active-Low Clear DAC Input. Pull CLR low to clear the input and DAC registers and set the DAC output to midscale (8000 hex), if MID/ ZERO is high, or zero scale (0000 hex), if MID/ ZERO is low. 24 MID/ ZERO Midscale/Zero-Scale Clear Output Value Select. Pull MID/ ZERO low for zero-scale clear output (0000 hex) or high for midscale clear output (8000 hex). 25 MTAP Internal Scaling Resistor Midpoint Tap. Connect to the inverting input of an external op amp. 26 INB Internal Resistor Input B. Free end of internal resistor (RINB). Connect to the output of an external output buffer for bipolar operation. 27 AVDD Analog Supply. Bypass AVDD to AGND with a 0.1µF capacitor as close to the device as possible. 28 AGND Analog Ground 29 INA Internal Resistor Input A. Free end of internal resistor (RINA). Connect to REF for bipolar operation. |
|
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |