8.1.2 Capacitive Loads

For capacitive loads under 100 pF, the propagation delay has minimum change (see Propagation Delay vs.

Capacitive Load). However, excessive capacitive loading under high switching frequencies may increase supply

current, propagation delay, or induce decreased slew rate.

8.1.3 Latch Functionality

The latch pin for the TLV3603-Q1 holds the output state of the device when the voltage at the LE/HYS pin is

a logic low. This is particularly useful when the output state is intended to remain unchanged. An important

consideration of the latch functionality is the latch hold and setup times. Latch hold time is the minimum time

required (after the latch pin is asserted) for properly latching the comparator output. Likewise, latch setup time is

defined as the time that the input must be stable before the latch pin is asserted low. The figure below illustrates

when the input can transition for a valid latch. Note that the typical setup time in the EC table is negative; this is

output response is shown below when the TLV3603-Q1 exits a latched output stage.

Invalid Input

Transition Region

Valid Input Transition

Region

Valid Input

Transition Region

LE/HYS

IN

Figure 8-3. Input Change Properly Latched

LE/HYS

IN

t

PL

OUT

Figure 8-4. Latch Disable with Input Change

8.2 Typical Application

8.2.1 Implementing Hysteresis

A comparator may produce “chatter” (multiple transitions) at the output when there are noise or signal variations

around the reference threshold; this causes the output to change states in rapid random successions as the

comparator input goes above and below the threshold of the reference. This usually occurs when the input signal

TLV3601-Q1, TLV3603-Q1

SNOSDC3B – JUNE 2021 – REVISED NOVEMBER 2021

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