8.2.4 External Trigger Function for Oscilloscopes

Below is a typical configuration for creating an external trigger on oscilliscopes. The user adjusts the trigger

level by programming a DAC that the TLV3601-Q1 and TLV3603-Q1 can use as a reference. The input from an

oscilloscope channel is then compared to the trigger reference voltage, and the comparator sends a signal to a

downstream FPGA to begin a capture.

FPGA

TLV3601

DAC

-

+

+

–

Trigger Input

Figure 8-11. External Trigger Function

9 Power Supply Recommendations

The TLV3601-Q1 and TLV3603-Q1 are specified for operation from 2.4 V to 5.5 V. While most applications

will require single supply operation where VEE is connected to the ground plane and VCC is connected to

the intended power supply level, the comparators can also be operated with split supplies. One caution when

using split supplies is that the output logic levels are determined by the VCC and VEE levels. For example, if

split supplies of +/- 2.5V are used, the output levels will be 2.5V and -2.5V accordingly. In addition, the logic

level of the LE/HYS pin will also be referenced to VEE. This means that the external hysteresis resistor on the

TLV3603-Q1 needs to be connected between the LE/HYS pin and VEE (not to ground) for proper operation.

Regardless of single supply or split supply operation, proper decoupling capacitors are required. It is

recommended to use a scheme of multiple, low-ESR ceramic capacitors from the supply pins to the ground

plane for optimum performance. A good combination would be 100 pF, 10 nF, and 1 uF with the lowest value

capacitor closest to the comparator.

TLV3601-Q1, TLV3603-Q1

SNOSDC3B – JUNE 2021 – REVISED NOVEMBER 2021

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