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MAX9290 Datasheet(PDF) 13 Page - Maxim Integrated Products

Part # MAX9290
Description  3.12Gbps GMSL Deserializers for Coax or STP Input and MIPI CSI-2 Output
PDF  103 Pages
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Manufacturer  MAXIM [Maxim Integrated Products]
Direct Link  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

MAX9290 Datasheet(HTML) 13 Page - Maxim Integrated Products

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(VAVDD18 = VDVDD18 = 1.7V to 1.9V, VAVDD3 = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100Ω ±1% (differential), EP connected
to PCB ground (GND), TA = -40°C to +105°C, unless otherwise noted. Typical values are at VAVDD18 = VDVDD18 = VIOVDD = 1.8V,
VAVDD3 = 3.3V, TA = +25°C.)
MAX9288/MAX9290
3.12Gbps GMSL Deserializers
for Coax or STP Input and MIPI CSI-2 Output
www.maximintegrated.com
Maxim Integrated │ 13
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Data Valid Acknowledge Time
tVD:ACK fSCL range
Low
3.45
µs
Mid
0.9
High
0.45
Pulse Width of Spikes
Suppressed
tSP
fSCL range
Low
50
ns
Mid
50
High
50
Capacitive Load Each Bus Line
Cb
(Note 8)
100
pF
SWITCHING CHARACTERISTICS (Note 10)
Deserializer Delay
tSD
(Note 11) Figure 8
1388
1500
Bits
Reverse Control-Channel
Output Rise Time
tR
No forward channel data transmission,
Figure 2
180
400
ns
Reverse Control-Channel
Output Fall Time
tF
No forward channel data transmission,
Figure 2
180
400
ns
GPI-to-GPO Delay
tGPIO
Deserializer GPI to serializer GPO (cable
delay not included), Figure 9
350
µs
Lock Time
tLOCK
Figure 10 (Note 12)
4
ms
Power-Up Time
tPU
Figure 11
8.5
ms
I2S/TDM OUTPUT TIMING (Note 10)
WS Jitter
tjWS
tWS = 1/fWS,
(cycle-to-cycle),
rising-to-falling
edge or falling-to-
rising edge
fWS = 48kHz or
44.1kHz
1.2e-3
x tWS
1.5e-3
x tWS
ns
fWS = 96kHz
1.6e-3
x tWS
2e-3
x tWS
fWS = 192kHz
1.6e-3
x tWS
2e-3 x
tWS
SCK Jitter (2-Channel I2S)
tjSCK1
tSCK = 1/fSCK,
(cycle-to-cycle),
rising-to-rising
edge
nSCK = 16 bits,
fWS = 48kHz or
44.1kHz
13e-3
x tSCK
16e-3
x tSCK
ns
nSCK = 24 bits,
fWS = 96kHz
39e-3
x tSCK
48e-3
x tSCK
nSCK = 32 bits,
fWS = 192kHz
0.1 x
tSCK
0.13 x
tSCK
SCK Jitter (8-Channel TDM)
tjSCK2
tSCK = 1/fSCK,
(cycle-to-cycle),
rising-to-rising
edge
nSCK = 16 bits,
fWS = 48kHz or
44.1kHz
52e-3
x tSCK
64e-3
x tSCK
ns
nSCK = 24 bits,
fWS = 96kHz
156e-3
x tSCK
192e-3
x tSCK
nSCK = 32 bits,
fWS = 192kHz
0.4 x
tSCK
0.52 x
tSCK
AC Electrical Characteristics (continued)



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