MAX9290 datasheet(21/103 Pages) MAXIM

21 / 103 page

MAX9288/MAX9290

3.12Gbps GMSL Deserializers

for Coax or STP Input and MIPI CSI-2 Output

www.maximintegrated.com

Maxim Integrated │ 21

NAME

FUNCTION

DRS

Data-Rate Select Input. DRS is latched upon power-up or when PWDN transitions low-to-high. Set

DRS high for pixel clock rates below 16.66MHz (BWS = low), 12.5MHz (BWS = high), or 36.66MHz

(BWS = open). Set DRS = low for faster pixel clock rates.

LFLT

Active-Low Open-Drain Line-Fault Output. LFLT has a 60kΩ internal pullup to IOVDD. LFLT = low

indicates a line fault. LFLT is high when PWDN = low.

LMN0

Line Fault Monitor Input 0 (See Figure 1)

LMN1

Line Fault Monitor Input 1 (See Figure 1)

CX/TP

Three-Level Coax/Twisted Pair Select Input. Use 6kΩ (max) pullup to IOVDD or pulldown resistor for

setting CX/TP = high or low. See Table 12 for function.

—

Exposed Pad. EP is internally connected to device ground.

MUST connect EP to the PCB ground plane

through an array of vias for proper thermal and electrical performance.

SERIAL TO

PARALLEL

FIFO

PARALLEL

TO CSI-2

I2S/TDM

RGB

CNTL[3:0]

(9B10B)

CLK±

DOUT0±

DOUT1±

DOUT2±

DOUT3±

PWDN BWS

REVERSE

CONTROL

CHANNEL

VIDEO

MAX9288

MAX9290

IN+

IN-

CLKDIV

HDCP

DECRYPT

HDCP

DECRYPT

HDCP

KEYS

CDRPLL

HDCP

CONTROL

FCC

ACB

SCK

CML RX

AND EQ

ADD[2:0]

8B/10B

DECODE/

DESCRAMBLE

(MAX9290

ONLY)

CONTROL

(9B10B)

SYNC

UART/I2C

TX/

SCL

RX/

SDA

GPIO_

GPI

I2CSEL

ADD0/CNTL0,

HIM/CNTL1,

ADD2/CNTL2,

ADD1/CNTL3

DATA DESCRIPTION

REGISTERS

INTOUT

CONTROL

CX/TP

ADD[2:0],

HIM

CDS

EQS

PLL

Pin Description (continued)

Functional Diagram

MAX9290 Datasheet(PDF) 21 Page - Maxim Integrated Products

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