AD7475ARMZ datasheet(7/24 Pages) AD

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Data Sheet

AD7475/AD7495

Rev. D | Page 7 of 24

TIMING SPECIFICATIONS1

VDD = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, REF IN = 2.5 V (AD7475), TA = TMIN to TMAX, unless otherwise noted.

Table 3.

Parameter

Limit at TMIN, TMAX

Unit

Description

fSCLK2

kHz min

MHz max

tCONVERT

16 × tSCLK

tSCLK = 1/fSCLK

800

ns max

fSCLK = 20 MHz

tQUIET

100

ns min

Minimum quiet time required between conversions

ns min

CS to SCLK setup time

t33

ns max

Delay from CS until SDATA three-state disabled

t43

ns max

Data access time after SCLK falling edge

0.4 tSCLK

ns min

SCLK low pulse width

0.4 tSCLK

ns min

SCLK high pulse width

ns min

SCLK to data valid hold time

t84

ns min

SCLK falling edge to SDATA high impedance

ns max

SCLK falling edge to SDATA high impedance

t94

ns max

CS rising edge to SDATA high impedance

tPOWER-UP

µs max

Power-up time from full power-down (AD7475)

650

µs max

Power-up time from full power-down (AD7495)

Guaranteed by initial characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V.

Mark/space ratio for the SCLK input is 40/60 to 60/40.

Measured with the load circuit of Figure 4 and defined as the time required for the output to cross 0.8 V or 2.0 V.

t8 and t9 are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 4. The measured number is

extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times, t8 and t9, quoted in the timing characteristics are

the true bus relinquish times of the device and are independent of the bus loading.

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