AD7475ARMZ datasheet(8/24 Pages) AD

8 / 24 page

AD7475/AD7495

Data Sheet

Rev. D | Page 8 of 24

TIMING EXAMPLE 1

With fSCLK = 20 MHz and a throughput of 1 MSPS, the cycle

time is t2 + 12.5(1/fSCLK) + tACQ = 1 µs. With t2 = 10 ns min, tACQ

is 365 ns. The 365 ns satisfies the requirement of 300 ns for tACQ.

In Figure 3, tACQ comprises 2.5(1/fSCLK) + t8 + tQUIET, where t8 = 45 ns.

This allows a value of 195 ns for tQUIET, satisfying the minimum

requirement of 100 ns.

TIMING EXAMPLE 2

With fSCLK = 5 MHz and a throughput of 315 KSPS, the cycle

time is t2 + 12.5(1/fSCLK) + tACQ = 3.174 µs. With t2 = 10 ns min,

tACQ is 664 ns. The 664 ns satisfies the requirement of 300 ns for

tACQ. In Figure 3, tACQ comprises 2.5(1/fSCLK) + t8 + tQUIET, where

t8 = 45 ns. This allows a value of 119 ns for tQUIET, satisfying the

minimum requirement of 100 ns. As in this example and with

other slower clock values, the signal may be acquired before the

conversion is complete, but it is still necessary to leave 100 ns

minimum tQUIET between conversions. In Example 2, the signal

is acquired at approximately Point C in Figure 3.

SCLK

SDATA

FOUR LEADING ZEROS

THREE-STATE

tQUIET

tCONVERT

THREE-STATE

DB11

DB10

DB2

DB0

DB1

Figure 2. Serial Interface Timing Diagram

SCLK

tQUIET

tCONVERT

45ns

tACQUISITION

12.5 (1/fSCLK)

10ns

1/THROUGHPUT

Figure 3. Serial Interface Timing Example

200

µA

IOL

200

µA

IOH

50pF

TO OUTPUT

1.6V

Figure 4. Load Circuit for Digital Output Timing Specifications

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