AM2634 datasheet(2/140 Pages) TI

2 / 140 page

Security:

• Hardware Security Module (HSM) with support for

Auto SHE 1.1/EVITA

• Secure boot support

– Device Take Over Protection

– Hardware-enforced root-of-trust

– Authenticated boot

– S/W Anti-rollback Protection

• Debug security

– Debug of HS device allowed only with proper

authentication

– Provision to disable debug

• Device ID and Key Management

– Support for OTP Memory (FUSEROM) to store

Root Keys & other security enabling fields

– Separate EFUSE controllers and FUSE ROMs

– Unique Device Public IDs

• Memory Protection Units (MPU)

– Arm® MPU present inside each Cortex®-R5F

core

– System MPU – present at various interfaces in

the SoC (can be a firewall or MPU)

• 8-16 Regions

• Programmable (Privilege ID, Read/Write/

Cachable, Start/End Address, Enable,

Secure/Non Secure)

• Cryptographic acceleration

– Supports cryptographic cores

• AES - 128/192/256 bits key sizes

• SHA2 - 256/384/512 bit support

• DRBG with Pseudo and True Random

number generator

• PKA (public key accelerator) to assist in

RSA/ECC processing

– DMA support

High-Speed Interfaces:

• Integrated Ethernet switch supporting two external

ports

– RMII(10/100) or RGMII (10/100/1000)

– IEEE1588 (2008 Annex D, Annex E, Annex F)

with 802.1AS PTP

– Clause 45 MDIO PHY management

– Packet Classifier based on ALE engine with

512 classifiers

– Priority based flow control

– Packet size up to 2KB

– Four CPU H/W interrupt Pacing

– IP/UDP/TCP checksum offload in hardware

Connectivity:

• 6x Universal Asynchronous Receiver-Transmitters

(UART)

• 5x Serial Peripheral Interface (SPI) controllers

• 5x Local Interconnect Network (LIN) ports

• 4x Inter-Integrated Circuit (I2C) ports

• 4x Modular Controller Area Network (MCAN)

modules with CAN-FD support

• 1x Quad Serial Peripheral Interface (QSPI)

• Fast Serial Interface (FSI) with 4x receiver cores

and 4x transmitter cores

• Up to 140 General-Purpose I/O (GPIO) pins

Media and Data Storage:

• 1x Multi-Media Card/Secure Digital (MMC/SD) 4-

bit interface

• General-Purpose Memory Controller (GPMC)

– 16-bit parallel data bus

– 22-bit address bus

– Up to 4MB addressable memory space

– Integrated Error Location Module (ELM)

support for error checking

Technology / Package:

• 45-nm technology

• 15mm x 15mm, 0.8-mm pitch, 324-pin NFBGA

2 Applications

• Single & Multi Axis Servo Drives

• AC Inverter & VF Drives

• Solar Energy

• EV Charging

• Renewable Energy Storage

• Traction Inverters

• Onboard Chargers

• DC-DC Converters

• Battery Management Systems

• Combo Box Architectures

• IO Aggregators

• Domain Controllers

AM2634, AM2634-Q1

SPRSP74 – MARCH 2022

www.ti.com

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