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ADFS5758

Data Sheet

Rev. 0 | Page 42 of 75

USE OF KEY CODES

The use of key codes (via the key register) allows direct access

to functions while keeping the user configuration register space

locked as read only. This functionality is contained within one

section for full details).

•

Initiate calibration memory refresh

•

Lock and unlock the user configuration register space.

•

Initiate a software reset.

•

Initiate a single ADC conversion.

•

Watchdog timer reset keys.

•

Recalculation of the background CRC diagnostic feature.

As well as enabling device access while the user configuration

such as a calibration memory refresh or a device reset provides

extra system robustness because it reduces the probability of

either of these tasks being initiated in error.

SOFTWARE RESET

A software reset requires two consecutive writes of 0x15FA and

0xAF51 to the key register. A device reset can be initiated via

the hardware RESET pin, the software reset keys, or automatically

after a WDT timeout (if configured to do so). The RESET_

OCCURRED bit in the DIGITAL_DIAG_RESULTS register is

set whenever the device is reset. This bit defaults to 1 on power-

up. Both of the diagnostic results registers implement a write 1 to

clear feature. That is, a 1 must be written to this bit to clear it (see

the Sticky Diagnostic Results Bits section).

CALIBRATION MEMORY CRC

For every calibration memory refresh cycle (which is initiated

via a key code write to the key register or automatically initiated

when the range bits, Bits[3:0] of the DAC_CONFIG register,

are changed), an automatic CRC is calculated on the contents

of the calibration memory shadow registers. The result of this

CRC is compared with the factory stored reference CRC value.

If the CRC values match, the read of the entire calibration

memory is considered valid. If they do not match, the CAL_

MEM_CRC_ERR bit in the DIGITAL_DIAG_RESULTS

be disabled via the CAL_MEM_CRC_EN bit in the

DIGITAL_DIAG_CONFIG register.

While this calibration memory refresh cycle is active, two-stage

readback commands are permitted, but a write to any register

(other than the TWO_STAGE_READBACK_SELECT register

or the NOP register) causes the INVALID_SPI_ACCESS_ERR

bit in the DIGITAL_DIAG_RESULTS register to set. As described

in the Echo Mode section, a wait period of 500 µs is recommended

after a calibration memory refresh cycle is initiated.

BACKGROUND CRC CHECK

After the device powers up, it is possible for the user to initiate a

background CRC calculation of the combined calibration memory

and register configuration space. Note that such a background

CRC calculation is enabled only when the configuration space

is locked. Any attempt to initiate a CRC calculation when the

configuration space is unlocked is ignored. When the config-

uration space is locked (see the Lockable User Configuration

Space section), a CRC is automatically calculated in the back-

ground and stored as the ideal CRC value that all subsequent

background CRC calculations are compared to. The back-

ground CRC calculation takes approximately 6 µs to complete.

A CRC check is configured by setting the relevant bits in the

DIGITAL_DIAG_CONFIG register. There are three

approaches to enable such a CRC check, as follows:

•

Initiate a CRC recalculation upon issuing a specific key

(default).

•

Enable an autocheck of the CRC to be performed on

completion of any valid SPI frame.

•

Enable continuous monitor mode to continually

recalculate the CRC in the background when enabled.

INTERNAL OSCILLATOR DIAGNOSTICS

An internal frequency monitor uses the internal oscillator (MCLK)

to increment a 16-bit counter at a rate of 1 kHz (MCLK/10,000).

The value of the counter is available to be read in the FREQ_

MONITOR register. The user can poll this register periodically

and use it both as a diagnostic tool for the internal oscillator

(to monitor that the oscillator is running), and to measure the

frequency. This feature is enabled by default via the FREQ_

MON_EN bit in the DIGITAL_DIAG_CONFIG register.

In the event that the internal MCLK oscillator stops, the

ADFS5758 sends a specific code of 0x07DEAD to the SDO line

for every SPI frame. This feature is enabled by default and can

be disabled by clearing the OSC_STOP_DETECT_EN bit in the

GP_CONFIG1 register. Note that this feature is limited to the

maximum readback timing specifications as outlined in Table 3.

ADR3425 Datasheet(PDF) 42 Page - Analog Devices

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