71M6541DSLASHFSLASHG datasheet(32/166 Pages) MAXIM

32 / 166 page

71M6541D/F/G and 71M6542F/G Data Sheet

Rev 5

To change the slot assignments established by MUXn_SEL[3:0], first set MUX_DIV[3:0] to zero,

then change the MUXn_SEL[3:0] slot assignments, and finally set MUX_DIV[3:0] to the number

of active MUX frame slots.

The 80515 writes into external data memory when the MPU executes a MOVX @Ri,A or MOVX

@DPTR,A instruction. The MPU reads external data memory by executing a MOVX A,@Ri or MOVX

A,@DPTR instruction (PDATA, SFR 0xBF, provides the upper 8 bytes for the MOVX A,@Ri instruction).

Internal and External Memory Map

Table 10 shows the address, type, use and size of the various memory components.

Table 10: Memory Map

Address

(hex)

Memory

Technology

Memory

Type

Name

Typical Usage

Memory Size

(bytes)

0000-7FFF

Flash Memory

Non-volatile

Program memory

for MPU and CE

MPU Program and

non-volatile data

128/64/32 KB

†

CE program (on 1

KB boundary)

3 KB max.

0000-0BFF

Static RAM

Volatile

External RAM

(XRAM)

Shared by CE and

MPU

5/3 KB

†

2000-27FF

Static RAM

Volatile

Configuration

RAM (I/O RAM)

Hardware control

2 KB

2800-287F

Static RAM

Non-volatile

(battery)

Configuration

RAM (I/O RAM)

Battery-buffered

memory

128

0000-00FF

Static RAM

Volatile

Internal RAM

Part of 80515 Core

256

† Memory size depends on IC. See 2.5.1 Physical Memory for details.

MOVX Addressing

There are two types of instructions differing in whether they provide an 8-bit or 16-bit indirect address to

the external data RAM.

In the first type, MOVX A,@Ri, the contents of R0 or R1 in the current register bank provide the eight

lower-ordered bits of address. The eight high-ordered bits of the address are specified with the PDATA

SFR. This method allows the user paged access (256 pages of 256 bytes each) to all ranges of the

external data RAM.

In the second type of MOVX instruction, MOVX A,@DPTR, the data pointer generates a 16-bit address.

This form is faster and more efficient when accessing very large data arrays (up to 64 KB), since no

additional instructions are needed to set up the eight high ordered bits of the address.

It is possible to mix the two MOVX types. This provides the user with four separate data pointers, two

with direct access and two with paged access, to the entire external memory range.

Dual Data Pointer

The Dual Data Pointer accelerates the block moves of data. The standard DPTR is a 16-bit register that

is used to address external memory or peripherals. In the 80515 core, the standard data pointer is called

DPTR, the second data pointer is called DPTR1. The data pointer select bit, located in the LSB of the DPS

selected when DPS[0] = 1.

The user switches between pointers by toggling the LSB of the DPS register. The values in the data pointers

are not affected by the LSB of the DPS register. All DPTR related instructions use the currently selected

DPTR for any activity.

The second data pointer may not be supported by certain compilers.

71M6541D/F/G Datasheet(PDF) 32 Page - Maxim Integrated Products

71M6541D/F/G Datasheet(HTML) 32 Page - Maxim Integrated Products

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL