71M6541DSLASHFSLASHG datasheet(44/166 Pages) MAXIM

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71M6541D/F/G and 71M6542F/G Data Sheet

Rev 5

External MPU Interrupts

The seven external interrupts are the interrupts external to the 80515 core, i.e., signals that originate in

other parts of the 71M654x, for example the CE, DIO, RTC, or EEPROM interface.

The external interrupts are connected as shown in Table 32. The polarity of interrupts 2 and 3 is

programmable in the MPU via the I3FR and I2FR bits in T2CON (SFR 0xC8). Interrupts 2 and 3 should be

programmed for falling sensitivity (I3FR = I2FR = 0). The generic 8051 MPU literature states that interrupts 4

through 6 are defined as rising-edge sensitive. Thus, the hardware signals attached to interrupts 5

and 6 are inverted to achieve the edge polarity shown in Table 32.

Table 32: External MPU Interrupts

External

Interrupt

Connection

Polarity

Flag Reset

Digital I/O (IE0)

see 2.5.8

automatic

Digital I/O (IE1)

see 2.5.8

automatic

CE_PULSE (IE_XPULSE, IE_YPULSE, IE_WPULSE,

IE_VPULSE)

rising

manual

CE_BUSY (IE3)

falling

automatic

VSTAT (VSTAT[2:0] changed) (IE4)

rising

automatic

EEPROM busy (falling), SPI (rising) (IE_EEX, IE_SPI)

—

manual

XFER_BUSY (falling), RTC_1SEC, RTC_1MIN, RTC_T

(IE_XFER, IE_RTC1S, IE_RTC1M, IE_RTCT)

falling

manual

External interrupt 0 and 1 can be mapped to pins on the device using DIO resource maps. See 2.5.8

Digital I/O for more information.

SFR enable bits must be set to permit any of these interrupts to occur. Likewise, each interrupt has its own

flag bit, which is set by the interrupt hardware, and reset by the MPU interrupt handler. XFER_BUSY,

RTC_1SEC, RTC_1MIN, RTC_T, SPI, PLLRISE and PLLFALL have their own enable and flag bits in

addition to the interrupt 6, 4 and enable and flag bits (see Table 33: Interrupt Enable and Flag Bits).

IE0 through IEX6 are cleared automatically when the hardware vectors to the interrupt handler.

The other flags, IE_XFER through IE_VPULSE, are cleared by writing a zero to them.

Since these bits are in an SFR bit addressable byte, common practice would be to clear them

with a bit operation, but this must be avoided. The hardware implements bit operations as a

byte wide read-modify-write hardware macro. If an interrupt occurs after the read, but before

the write, its flag cleared unintentionally.

The proper way to clear the flag bits is to write a byte mask consisting of all ones except for a

zero in the location of the bit to be cleared. The flag bits are configured in hardware to ignore

ones written to them.

71M6541D/F/G Datasheet(PDF) 44 Page - Maxim Integrated Products

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