71M6541DSLASHFSLASHG datasheet(39/166 Pages) MAXIM

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71M6541D/F/G and 71M6542F/G Data Sheet

Rev 5

Table 20: The S1CON (UART1) Register (SFR 0x9B)

Bit

Symbol

Function

S1CON[7]

Sets the baud rate and mode for UART1.

Mode

Description

Baud Rate

9-bit UART

variable

8-bit UART

variable

S1CON[5]

SM21

Enables the inter-processor communication feature.

S1CON[4]

REN1

If set, enables serial reception. Cleared by software to disable reception.

S1CON[3]

TB81

The 9

th transmitted data bit in Mode A. Set or cleared by the MPU,

depending on the function it performs (parity check, multiprocessor

communication etc.)

S1CON[2]

RB81

In Modes A and B, it is the 9

th data bit received. In Mode B, if SM21 is 0,

RB81 is the stop bit. Must be cleared by software

S1CON[1]

TI1

Transmit interrupt flag, set by hardware after completion of a serial transfer.

Must be cleared by software (see Caution above).

S1CON[0]

RI1

Receive interrupt flag, set by hardware after completion of a serial reception.

Must be cleared by software (see Caution above).

Table 21: PCON Register Bit Description (SFR 0x87)

Bit

Symbol

Function

PCON[7]

SMOD

The SMOD bit doubles the baud rate when set

2.4.6

Timers and Counters

The 80515 has two 16-bit timer/counter registers: Timer 0 and Timer 1. These registers can be configured

for counter or timer operations.

In timer mode, the register is incremented every machine cycle, i.e., it counts up once for every 12 periods

of the MPU clock. In counter mode, the register is incremented when the falling edge is observed at the

corresponding input signal T0 or T1 (T0 and T1 are the timer gating inputs derived from certain DIO pins,

see 2.5.8 Digital I/O). Since it takes 2 machine cycles to recognize a 1-to-0 event, the maximum input

count rate is 1/2 of the clock frequency (CKMPU). There are no restrictions on the duty cycle, however

to ensure proper recognition of the 0 or 1 state, an input should be stable for at least 1 machine cycle.

Four operating modes can be selected for Timer 0 and Timer 1, as shown in Table 22 and Table 23. The

TMOD (SFR 0x89) Register, shown in Table 24, is used to select the appropriate mode. The timer/counter

operation is controlled by the TCON (SFR 0x88) Register, which is shown in Table 25. Bits TR1 (TCON[6])

and TR0 (TCON[4]) in the TCON register start their associated timers when set.

71M6541D/F/G Datasheet(PDF) 39 Page - Maxim Integrated Products

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