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71M6541D/F/G and 71M6542F/G Data Sheet

Rev 5

Table 25: The TCON Register Bit Functions (SFR 0x88)

Bit

Symbol Function

TCON[7]

TF1

The Timer 1 overflow flag is set by hardware when Timer 1 overflows. This flag

can be cleared by software and is automatically cleared when an interrupt is

processed.

TCON[6]

TR1

Timer 1 run control bit. If cleared, Timer 1 stops.

TCON[5]

TF0

Timer 0 overflow flag set by hardware when Timer 0 overflows. This flag can be

cleared by software and is automatically cleared when an interrupt is processed.

TCON[4]

TR0

Timer 0 Run control bit. If cleared, Timer 0 stops.

TCON[3]

IE1

Interrupt 1 edge flag is set by hardware when the falling edge on external pin int1 is

observed. Cleared when an interrupt is processed.

TCON[2]

IT1

Interrupt 1 type control bit. Selects either the falling edge or low level on input pin

to cause an interrupt.

TCON[1]

IE0

Interrupt 0 edge flag is set by hardware when the falling edge on external pin int0 is

observed. Cleared when an interrupt is processed.

TCON[0]

IT0

Interrupt 0 type control bit. Selects either the falling edge or low level on input pin

to cause interrupt.

2.4.7

WD Timer (Software Watchdog Timer)

There is no internal software watchdog timer. Use the standard hardware watchdog timer instead (see

2.5.11 Hardware Watchdog Timer).

2.4.8

Interrupts

The 80515 provides 11 interrupt sources with four priority levels. Each source has its own

interrupt request

flag(s) located in a special function register (TCON, IRCON, and SCON). Each interrupt requested by

the corresponding interrupt flag can be individually enabled or disabled by the interrupt enable bits in the

IEN0 (SFR 0xA8), IEN1 (SFR 0xB8), and IEN2 (SFR 0x9A). Figure 16 shows the device interrupt structure.

Referring to Figure 16, interrupt sources can originate from within the 80515 MPU core (referred to as

Internal Sources) or can originate from other parts of the 71M654x SoC (referred to as External Sources).

There are seven external interrupt sources, as seen in the leftmost part of Figure 16, and in Table 26 and

Table 27 (i.e., EX0-EX6).

Interrupt Overview

When an interrupt occurs, the MPU vectors to the predetermined address as shown in Table 38. Once

the interrupt service has begun, it can be interrupted only by a higher priority interrupt. The interrupt service

is terminated by a return from interrupt instruction, RETI. When a RETI instruction is performed, the

processor returns to the instruction that would have been next when the interrupt occurred.

When the interrupt condition occurs, the processor also indicates this by setting a flag bit. This bit is set

regardless of whether the interrupt is enabled or disabled. Each interrupt flag is sampled once per

machine cycle, and then samples are polled by the hardware. If the sample indicates a pending interrupt

when the interrupt is enabled, then the interrupt request flag is set. On the next instruction cycle, the

interrupt is acknowledged by hardware forcing an LCALL to the appropriate vector address, if the

following conditions are met:

•

No interrupt of equal or higher priority is already in progress.

•

An instruction is currently being executed and is not completed.

•

The instruction in progress is not RETI or any write access to the registers IEN0, IEN1, IEN2, IP0 or IP1.

Special Function Registers for Interrupts

The following SFR registers control the interrupt functions:

•

The interrupt enable registers: IEN0, IEN1 and IEN2 (see Table 26, Table 27 and Table 28).

•

The Timer/Counter control registers, TCON and T2CON (see

•

Table 29 and Table 30).

•

The interrupt request register, IRCON (see Table 31).

71M6541D/F/G Datasheet(PDF) 41 Page - Maxim Integrated Products

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