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MPC8315ECVRADDA Datasheet(PDF) 3 Page - NXP Semiconductors |
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MPC8315ECVRADDA Datasheet(HTML) 3 Page - NXP Semiconductors |
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3 / 106 page  MPC8315E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 3 MPC8315E Features • 16-Kbyte instruction cache, 16-Kbyte data cache • One floating point unit and two integer units • Software-compatible with the Freescale processor families implementing the PowerPC Architecture • Performance monitor 2.2 Serial Interfaces The following interfaces are supported in the MPC8315E. • Two enhanced TSECs (eTSECs) • Two Ethernet interfaces using one RGMII/MII/RMII/RTBI or SGMII (no GMII) • Dual UART, one I2C, and one SPI interface 2.3 Security Engine The security engine is optimized to handle all the algorithms associated with IPSec, 802.11i, and iSCSI. The security engine contains one crypto-channel, a controller, and a set of crypto execution units (EUs). The execution units are: • Public key execution unit (PKEU) — RSA and Diffie-Hellman (to 4096 bits) — Programmable field size up to 2048 bits — Elliptic curve cryptography (1023 bits) — F2m and F(p) modes — Programmable field size up to 511 bits • Data encryption standard execution unit (DEU) — DES, 3DES — Two key (K1, K2) or three key (K1, K2, K3) — ECB, CBC, CFB-64 and OFB-64 modes for both DES and 3DES • Advanced encryption standard unit (AESU) — Implements the Rinjdael symmetric key cipher — Key lengths of 128, 192, and 256 bits — ECB, CBC, CCM, CTR, GCM, CMAC, OFB, CFB, XCBC-MAC and LRW modes — XOR acceleration • Message digest execution unit (MDEU) — SHA with 160-bit, 256-bit, 384-bit and 512-bit message digest — SHA-384/512 — MD5 with 128-bit message digest — HMAC with either algorithm • Random number generator (RNG) |
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