MIMXRT406LCJM4A datasheet(41/72 Pages) NXP

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Electrical characteristics

i.MX RT1015 Crossover Processors Data Sheet for Consumer Products, Rev. 3.1, 03/2022

NXP Semiconductors

Figure 19. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case B1)

Figure 20. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case B2)

4.5.1.1

FlexSPI output/write timing

The following sections describe output signal timing for the FlexSPI controller including control signals

and data outputs.

4.5.1.1.1

SDR mode

Table 36. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case B2)

Symbol

Parameter

Min

Max

Unit

—

Frequency of operation

—

166

MHz

TSCKD

Time from SCK to data valid

—

TSCKD - TSCKDQS

Time delta between TSCKD and TSCKDQS

-1

Table 37. FlexSPI output timing in SDR mode

Symbol

Parameter

Min

Max

Unit

—

Frequency of operation

—

1661

MHz

Tck

SCK clock period

6.0

—

TDVO

Output data valid time

—

TDHO

Output data hold time

-1

—

TSCKD

TSCKDQS

SIO[0:7]

DQS

SCK

TSCKD

TSCK2DQS

SCK2

SIO[0:7]

DQS

SCK

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