MPC5643L datasheet(115/136 Pages) NXP

115 / 136 page

Electrical characteristics

MPC5643L Microcontroller Data Sheet, Rev. 10

NXP Semiconductors

115

Figure 29. External interrupt timing

3.20.6

DSPI timing

Table 39. DSPI timing

No.

Symbol

Parameter

Conditions

Min

Max

Unit

1tSCK

DSPI cycle time

Master (MTFE = 0)

—

Slave (MTFE = 0)

—

Slave Receive Only Mode1

—

2tCSC

PCS to SCK delay

—

3tASC

After SCK delay

—

4tSDC

SCK duty cycle

—

tSCK/2 - 10 tSCK/2 + 10 ns

5tA

Slave access time

SS active to SOUT valid

—

6tDIS

Slave SOUT disable time

SS inactive to SOUT High-Z or invalid

—

7tPCSC

PCSx to PCSS time

—

8tPASC

DPCSS to PCSx time

—

9tSUI

Data setup time for inputs

Master (MTFE = 0)

—

Slave

2—

Master (MTFE = 1, CPHA = 0)

5—

Master (MTFE = 1, CPHA = 1)

—

tHI

Data hold time for inputs

Master (MTFE = 0)

–5

—

Slave

—

Master (MTFE = 1, CPHA = 0)

—

Master (MTFE = 1, CPHA = 1)

–5

—

tSUO

Data valid (after SCK edge)

Master (MTFE = 0)

—

Slave

—

Master (MTFE = 1, CPHA = 0)

—

Master (MTFE = 1, CPHA = 1)

—

IRQ

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