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AD10465PCB Datasheet(PDF) 3 Page - Analog Devices |
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AD10465PCB Datasheet(HTML) 3 Page - Analog Devices |
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3 / 20 page ![]() REV. 0 –3– AD10465 Test Mil AD10465AZ/BZ/QML-H Parameter Temp Level Subgroup Min Typ Max Unit SPURIOUS-FREE DYNAMIC RANGE 8 Analog Input @ 4.98 MHz 25 °C V 85 dBFS Analog Input @ 9.9 MHz 25 °C I 4 73 82 dBFS Full II 5, 6 70 82 dBFS Analog Input @ 19.5 MHz 25 °C I 4 72 78 dBFS Full II 5, 6 70 78 dBFS Analog Input @ 32.1 MHz 25 °C I 4 62 68 dBFS Full II 5, 6 60 66 dBFS TWO-TONE IMD REJECTION 9 fIN = 10 MHz and 11 MHz 25 °C I 4 78 87 dBFS f1 and f2 are –7 dB II 5, 6 78 fIN = 31 MHz and 32 MHz 25 °C I 4 68 70 dBFS f1 and f2 Are –7 dB Full II 5, 6 60 CHANNEL-TO-CHANNEL ISOLATION 10 25 °CIV 12 90 dB TRANSIENT RESPONSE 25 °C V 15.3 ns OVERVOLTAGE RECOVERY TIME 11 VIN = 2.0 × f S Full IV 12 40 100 ns VIN = 4.0 × f S Full IV 12 150 200 ns DIGITAL OUTPUTS 12 Logic Compatibility CMOS DVCC = 3.3 V Logic “1” Voltage Full I 1, 2, 3 2.5 DVCC – 0.2 V Logic “0” Voltage Full I 1, 2, 3 0.2 0.5 V DVCC = 5 V Logic “1” Voltage Full V DVCC – 0.3 V Logic “0” Voltage Full V 0.35 V Output Coding Two’s Complement POWER SUPPLY AVCC Supply Voltage 13 Full VI 4.85 5.0 5.25 V I (AVCC) Current Full I 270 308 mA AVEE Supply Voltage 13 Full VI –5.25 –5.0 –4.75 V I (AVEE) Current Full V 38 49 mA DVCC Supply Voltage 13 Full VI 3.135 3.3 3.465 V I (DVCC) Current Full V 30 46 mA ICC (Total) Supply Current per Channel Full I 1, 2, 3 338 403 mA Power Dissipation (Total) Full I 1, 2, 3 3.5 3.9 W Power Supply Rejection Ratio (PSRR) Full V 0.02 % FSR/% VS Passband Ripple to 10 MHz V 0.1 dB Passband Ripple to 25 MHz V 0.2 dB NOTES 1 Gain tests are performed on A IN1 input voltage range. 2 Input Capacitance spec. combines AD8037 die capacitance and ceramic package capacitance. 3 Full power bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB. 4 All ac specifications tested by driving ENCODE and ENCODE differentially. 5 Minimum and maximum conversion rates allow for variation in Encode Duty Cycle of 50% ± 5%. 6 Analog input signal power at –1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first five harmonics removed). Encode = 65 MSPS. SNR is reported in dBFS, related back to converter full power. 7 Analog input signal power at –1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. Encode = 65 MSPS. 8 Analog input signal power swept from –1 dBFS to –60 dBFS; SFDR is ratio of converter full scale to worst spur. 9 Both input tones at –7 dBFS; two-tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third order intermod product. 10 Channel-to-channel isolation tested with A channel grounded and a full-scale signal applied to B channel. 11 Input driven to 2 × and 4× A IN1 range for > four clock cycles. Output recovers inband in specified time with Encode = 65 MSPS. 12 Digital output logic levels: DV CC = 3.3 V, CLOAD = 10 pF. Capacitive loads > 10 pF will degrade performance. 13 Supply voltage recommended operating range. AV CC may be varied from 4.85 V to 5.25 V. However, rated ac (harmonics) performance is valid only over the range AVCC = 5.0 V to 5.25 V. All specifications guaranteed within 100 ms of initial power-up regardless of sequencing. Specifications subject to change without notice. |
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