LPC2103 datasheet(15/32 Pages) PHILIPS

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LPC2101_02_03_1

Preliminary data sheet

Rev. 01 — 18 January 2006

15 of 32

Philips Semiconductors

LPC2101/2102/2103

Single-chip 16-bit/32-bit microcontrollers

• Combined SPI master and slave.

• Maximum data bit rate of one eighth of the input clock rate.

6.12 SSP serial I/O controller

The LPC2101/2102/2103 each contain one SSP. The SSP controller is capable of

operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and

slaves on the bus. However, only a single master and a single slave can communicate on

the bus during a given data transfer. The SSP supports full duplex transfers, with data

frames of 4 bits to 16 bits ﬂowing from the master to the slave and from the slave to the

master. Often only one of these data streams carries meaningful data.

6.12.1 Features

• Compatible with Motorola SPI, 4-wire TI’s SSI and National Semiconductor’s

Microwire buses.

• Synchronous Serial Communication.

• Master or slave operation.

• 8-frame FIFOs for both transmit and receive.

• Four bits to 16 bits per frame.

6.13 General purpose 32-bit timers/external event counters

The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an

externally supplied clock and optionally generate interrupts or perform other actions at

speciﬁed timer values, based on four match registers. It also includes four capture inputs

to trap the timer value when an input signal transitions, optionally generating an interrupt.

Multiple pins can be selected to perform a single capture or match function, providing an

application with ‘or’ and ‘and’, as well as ‘broadcast’ functions among them.

The LPC2101/2102/2103 can count external events on one of the capture inputs if the

minimum external pulse is equal or longer than a period of the PCLK. In this conﬁguration,

unused capture lines can be selected as regular timer capture inputs or used as external

interrupts.

6.13.1 Features

• A 32-bit timer/counter with a programmable 32-bit prescaler.

• External event counter or timer operation.

• Four 32-bit capture channels per timer/counter that can take a snapshot of the timer

value when an input signal transitions. A capture event may also optionally generate

an interrupt.

• Four 32-bit match registers that allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

• Four external outputs per timer/counter corresponding to match registers, with the

following capabilities:

– Set LOW on match.

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