AD7405

Data Sheet

INPUT FILTER

In a typical application, where voltage is being measured across

a shunt resistor, connect the AD7405 directly across the shunt

resistor with a simple RC low-pass filter on each input.

The recommended circuit configuration for driving the

differential inputs to achieve best performance is shown in

Figure 27. An RC low-pass filter is placed on both the analog

input pins. Recommended values for the resistors and capacitors

are 10 Ω and 220 pF, respectively. If possible, equalize the

source impedance on each analog input to minimize offset.

Figure 27. RC Low-Pass Filter Input Network

The input filter configuration for the AD7405 is not limited to

the low-pass structure shown in Figure 27. The differential RC

filter configuration shown in Figure 28 also achieves excellent

performance. Recommended values for the resistors and

capacitor are 22 Ω and 47 pF, respectively.

Figure 28. Differential RC Filter Input Network

Figure 29 compares the typical performance for the input filter

structures outlined in Figure 27 and Figure 28 for different

resistor and capacitor values.

Figure 29. SNR vs. Decimation Rate for Different Filter Structures for Different

Resistor and Capacitor Values

DIGITAL FILTER

The output of the AD7405 is a continuous LVDS digital bit stream.

To reconstruct the original input signal information, this output

bit stream needs to be digitally filtered and decimated. A sinc

filter is recommended due to its simplicity. A sinc3 filter is

recommended because it is one order higher than that of the

AD7405 modulator, which is a second-order modulator. The type

of filter selected, the decimation rate, and the modulator clock used

determines the overall system resolution and throughput rate. The

higher the decimation rate, the greater the system accuracy, as

illustrated in Figure 30. However, there is a trade-off between

accuracy and throughput rate and, therefore, higher decimation

rates result in lower throughput solutions. Note that for a given

bandwidth requirement, a higher MCLKIN frequency can allow

higher decimation rates to be used, resulting in higher SNR

performance.

Figure 30. SNR vs. Decimation Rate for Different Sinc Filter Orders

A sinc3 filter is recommended for use with the AD7405. This

filter can be implemented on a field programmable gate array

(FPGA) or a digital signal processor (DSP).

Equation 1 describes the transfer function of a sinc filter.

(

)

(

)

N

DR

Z

Z

DR

z

H













−

−

=

−

−

1

1

1

1

)

(

(1)

where DR is the decimation rate and N is the sinc filter order.

The throughput rate of the sinc filter is determined by the

modulator clock and the decimation rate selected.

DR

MCLK

Throughput =

(2)

where MCLK is the modulator clock frequency

As the decimation rate increases, the data output size from the

sinc filter increases. The output data size is expressed

in Equation 3. The 16 most significant bits are used to return a

16-bit result.

(3)

R

R

C

C

AD7405

R

R

C

AD7405

50

55

60

65

70

75

80

85

90

95

10

100

1000

DECIMATION RATE

LOW PASS, 10Ω, 220pF

DIFFERENTIAL, 22Ω, 47pF

DIFFERENTIAL, 22Ω, 10nF

0

10

20

30

40

50

60

70

80

90

100

10

100

1000

DECIMATION RATE

SINC1

SINC2

SINC3

SINC4

Rev. A | Page 16 of 20