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AD7405 Datasheet(PDF) 3 Page - Analog Devices |
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AD7405 Datasheet(HTML) 3 Page - Analog Devices |
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3 / 20 page  Data Sheet AD7405 SPECIFICATIONS VDD1 = 4.5 V to 5.5 V, VDD2 = 3 V to 5.5 V, VIN+ = −250 mV to +250 mV, VIN− = 0 V, TA = −40°C to +125°C, fMCLKIN1 = 5 MHz to 20 MHz, tested with sinc3 filter, 256 decimation rate, as defined by Verilog code, unless otherwise noted. All voltages are relative to their respective ground. Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments STATIC PERFORMANCE Resolution 16 Bits Filter output truncated to 16 bits Integral Nonlinearity2 INL ±2 ±12 LSB Differential Nonlinearity2 DNL ±0.99 LSB Guaranteed no missing codes to 16 bits Offset Error2 ±0.2 ±0.75 mV Offset Drift vs. Temperature 1.6 3.8 µV/°C 1.3 3.1 µV/°C 0°C to 85°C Offset Drift vs. VDD1 50 µV/V Gain Error2 ±0.2 ±0.8 % FSR fMCLKIN = 16 MHz ±0.2 ±0.8 % FSR fMCLKIN = 20 MHz, TA = −40°C to +85°C ±0.2 ±1.2 % FSR fMCLKIN = 20 MHz Gain Error Drift vs. Temperature 65 95 ppm/°C 40 60 µV/°C Gain Error Drift vs. VDD1 ±0.6 mV/V ANALOG INPUT Input Voltage Range −320 +320 mV Full-scale range −250 +250 mV For specified performance Input Common-Mode Voltage Range −200 to +300 mV Dynamic Input Current ±45 ±50 µA VIN+ = ±250 mV, VIN− = 0 V 0.05 µA VIN+ = 0 V, VIN− = 0 V DC Leakage Current ±0.01 ±0.6 µA Input Capacitance 14 pF DYNAMIC SPECIFICATIONS VIN+ = 1 kHz Signal-to-Noise-and-Distortion Ratio2 SINAD 81 87 dB 83 87 dB −40°C to +85°C Signal-to-Noise Ratio2 SNR 86 88 dB Total Harmonic Distortion2 THD −96 dB Peak Harmonic or Spurious Noise2 SFDR −97 dB Effective Number of Bits2 ENOB 13.1 14.2 Bits 13.4 14.2 Bits −40°C to +85°C Noise Free Code Resolution2 14 Bits ISOLATION TRANSIENT IMMUNITY2 25 30 kV/µs LVDS I/O (ANSI-644) Differential Output Voltage VOD 247 360 454 mV RL = 100 Ω Common-Mode Output Voltage VOCM 1125 1260 1375 mV RL = 100 Ω Differential Input Voltage VID 150 650 mV Common-Mode Input Voltage VICM 800 1575 mV POWER REQUIREMENTS VDD1 4.5 5.5 V VDD2 3 5.5 V IDD1 30 36 mA VDD1 = 5.5 V IDD2 18 22 mA VDD2 = 5.5 V 13 15 mA VDD2 = 3.3 V Power Dissipation 264 319 mW VDD1 = VDD2 = 5.5 V 208 248 mW VDD1 = 5.5 V, VDD2 = 3.3 V 1 For fMCLKIN > 16 MHz, mark space ratio is 48/52 to 52/48, and VDD1 = 5 V ± 5%. 2 See the Terminology section. Rev. A | Page 3 of 20 |
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