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Data Sheet

AD7405

For a sinc3 filter, the −3 dB filter response point can be derived

from the filter transfer function, Equation 1, and is 0.262 times

the throughput rate. The filter characteristics for a third-order

sinc3 filter are summarized in Table 11.

Table 11. Sinc3 Filter Characteristics for 20 MHz MCLKIN

Decimation

Ratio (DR)

Throughput

Rate (kHz)

Output Data

Size (Bits)

Filter

Response (kHz)

625

163.7

312.5

81.8

128

156.2

40.9

256

78.1

20.4

512

39.1

10.2

The following Verilog code provides an example of a sinc3 filter

implementation on a Xilinx® Spartan®-6 FPGA. Note that the

data is read on the positive clock edge. It is recommended to

read in the data on the positive clock edge. The code is

configurable to accommodate decimation rates from 32 to 4096.

module dec256sinc24b

(

input mclk1,

/* used to clk filter */

input reset,

/* used to reset filter */

input mdata1, /* input data to be filtered

output reg [15:0] DATA, /* filtered output

output reg data_en,

input [15:0] dec_rate

);

/* Data is read on positive clk edge */

reg [36:0] ip_data1;

reg [36:0] acc1;

reg [36:0] acc2;

reg [36:0] acc3;

reg [36:0] acc3_d2;

reg [36:0] diff1;

reg [36:0] diff2;

reg [36:0] diff3;

reg [36:0] diff1_d;

reg [36:0] diff2_d;

reg [15:0] word_count;

reg word_clk;

reg enable;

/*Perform the Sinc action*/

always @ (mdata1)

if(mdata1==0)

ip_data1 <= 37'd0;

/* change 0 to a -1 for twos

complement */

else

ip_data1 <= 37'd1;

/*Accumulator (Integrator)

Perform the accumulation (IIR) at the speed

of the modulator.

Z = one sample delay MCLKOUT = modulators

conversion bit rate */

Figure 31. Accumulator

always @ (negedge mclk1, posedge reset)

begin

if (reset)

begin

/* initialize acc registers on reset

acc1 <= 37'd0;

acc2 <= 37'd0;

acc3 <= 37'd0;

end

else

begin

/*perform accumulation process */

acc1 <= acc1 + ip_data1;

acc2 <= acc2 + acc1;

acc3 <= acc3 + acc2;

end

/*decimation stage (MCLKOUT/WORD_CLK) */

always @ (posedge mclk1, posedge reset)

begin

if (reset)

word_count <= 16'd0;

else

begin

if ( word_count == dec_rate -

1 )

word_count <= 16'd0;

else

word_count <= word_count

+ 16'b1;

end

always @ ( posedge mclk1, posedge reset )

begin

if ( reset )

word_clk <= 1'b0;

else

begin

if ( word_count == dec_rate/2 -

1 )

word_clk <= 1'b1;

else if ( word_count ==

dec_rate - 1 )

word_clk <= 1'b0;

end

/*Differentiator (including decimation

stage)

Perform the differentiation stage (FIR) at a

lower speed.

MCLKIN

IP_DATA1

ACC1+

ACC2+

ACC3+

Rev. A | Page 17 of 20

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