LTM2810

19

Rev. A

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APPLICATIONS INFORMATION

Table 2. Bidirectional SPI Timing Event Description

TIME

CPHA

EVENT DESCRIPTION

0, 1

Asynchronous chip select, may be synchronous to SDI but may not lag by more than 3ns. Logic side slave data

output enabled, initial data is not equivalent to slave device data output.

0, 1

Propagation delay chip select, logic to isolated side, 50ns typical.

0, 1

Slave device chip select output data enable.

0

Start of data transmission, data setup.

1

Start of transmission, data and clock setup. Data transition must be within –13ns to 3ns of clock edge.

0, 1

Propagation delay of slave data, isolated to logic side, 50ns typical.

0, 1

Slave data output valid, logic side.

0

Propagation delay of data, logic side to isolated side.

1

Propagation delay of data and clock, logic side to isolated side.

0, 1

Logic side data sample time, half clock period delay from data setup transition.

0, 1

Propagation delay of clock, logic to isolated side.

0, 1

Isolated side data sample time.

0, 1

Synchronous data and clock transition, logic side.

0, 1

Data to clock delay, must be ≤ 13ns.

0, 1

Clock to data delay, must be ≤ 3ns.

0, 1

Propagation delay clock and data, logic to isolated side.

0, 1

Slave device data transition.

0, 1

Propagation delay slave data, isolated to logic side.

0, 1

Slave data output to sample clock setup time.

0

Last data and clock transition logic side.

1

Last sample clock transition logic side.

0

Propagation delay data and clock, logic to isolated side.

1

Propagation delay clock, logic to isolated side.

0

Last slave data output transition logic side.

1

Last slave data output and data transition, logic side.

1

Propagation delay data, logic to isolated side.

0, 1

Asynchronous chip select transition, end of transmission. Disable slave data output logic side.

0, 1

Chip select transition isolated side, slave data output disabled.