LTM2810

21

Rev. A

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APPLICATIONS INFORMATION

Table 3. Unidirectional SPI Timing Event Description

TIME

CPHA

EVENT DESCRIPTION

0, 1

Asynchronous chip select, may be synchronous to SDI but may not lag by more than 3ns.

0, 1

Propagation delay chip select, logic to isolated side.

0

Start of data transmission, data setup.

1

Start of transmission, data and clock setup. Data transition must be within –13ns to 3ns of clock edge.

0

Propagation delay of data, logic side to isolated side.

1

Propagation delay of data and clock, logic side to isolated side.

0, 1

Logic side data sample time, half clock period delay from data setup transition.

0, 1

Clock propagation delay, clock and data transition.

0, 1

Data to clock delay, must be ≤ 13ns.

0, 1

Clock to data delay, must be ≤ 3ns.

0, 1

Data and clock propagation delay.

0

Last clock and data transition.

1

Last clock transition.

0

Clock and data propagation delay.

1

Clock propagation delay.

1

Data propagation delay.

0, 1

Asynchronous chip select transition, end of transmission.

0, 1

Chip select transition isolated side.