AFE7900 datasheet(3/157 Pages) TI

3 / 157 page

4 Description (continued)

Each receiver chain includes a 25-dB range DSA (Digital Step Attenuator), followed by a 3-GSPS ADC (analog-

to-digital converter). Each receiver channel has an analog peak power detector and various digital power

detectors to assist an external or internal autonomous automatic gain controller, and RF overload detectors for

device reliability protection. Flexible decimation options provide optimization of data bandwidth up to 1200 MHz

for four RX without FB paths or 600 MHz with two FB paths (1200 MHz BW each).

The device contains a SYSREF timing detector to allow optimization of the SYSREF input timing relative to the

device clock.

5 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision * (February 2021) to Revision A (August 2021)

Page

• Added Feature to Request the full data sheet.................................................................................................... 1

• Added the Specification tables to the data sheet................................................................................................4

• Added the Typical Characteristics section to the data sheet............................................................................ 32

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AFE7900

SBASA44A – AUGUST 2021 – REVISED MARCH 2022

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AFE7900 Datasheet(PDF) 3 Page - Texas Instruments