Pin Descriptions

Pin Name

Pin

Number

I/O

Description

LINE SIDE HIGH SPEED DIFFERENTIAL IO’s

LI_0+

LI_0−

6

7

I

Inverting and non-inverting differential inputs of port_0 at the line side. LI_0+ and LI_0−

have an internal 50

Ω connected to an internal reference voltage.

LO_0+

LO_0−

33

34

O

Inverting and non-inverting differential outputs of port_0 at the line side. LO_0+ and LO_0−

have an internal 50

Ω connected to V

LI_1+

LI_1−

30

31

I

Inverting and non-inverting differential inputs of port_1 at the line side. LI_1+ and LI_1−

have an internal 50

Ω connected to an internal reference voltage.

LO_1+

LO_1−

9

10

O

Inverting and non-inverting differential outputs of port_1 at the line side. LO_1+ and LO_1−

have an internal 50

Ω connected to V

SWITCH SIDE HIGH SPEED DIFFERENTIAL IO’s

SOA_0+

SOA_0−

46

45

O

Inverting and non-inverting differential outputs of mux_0 at the switch_A side. SOA_0+ and

SOA_0− have an internal 50

Ω connected to V

SOB_0+

SOB_0−

4

3

O

Inverting and non-inverting differential outputs of mux_0 at the switch_B side. SOB_0+ and

SOB_0− have an internal 50

Ω connected to V

SIA_0+

SIA_0−

40

39

I

Inverting and non-inverting differential inputs to the mux_0 at the switch_A side. SIA_0+

and SIA_0− have an internal 50

Ω connected to an internal reference voltage.

SIB_0+

SIB_0−

43

42

I

Inverting and non-inverting differential inputs to the mux_0 at the switch_B side. SIB_0+

and SIB_0− have an internal 50

Ω connected to an internal reference voltage.

SOA_1+

SOA_1−

22

21

O

Inverting and non-inverting differential outputs of mux_1 at the switch_A side. SOA_1+ and

SOA_1− have an internal 50

Ω connected to V

SOB_1+

SOB_1−

28

27

O

Inverting and non-inverting differential outputs of mux_1 at the switch_B side. SOB_1+ and

SOB_1− have an internal 50

Ω connected to V

SIA_1+

SIA_1−

16

15

I

Inverting and non-inverting differential inputs to the mux_1 at the switch_A side. SIA_1+

and SIA_1− have an internal 50

Ω connected to an internal reference voltage.

SIB_1+

SIB_1−

19

18

I

Inverting and non-inverting differential inputs to the mux_1 at the switch_B side. SIB_1+

and SIB_1− have an internal 50

Ω connected to an internal reference voltage.

CONTROL (3.3V LVCMOS)

MUX_S0

37

I

A logic low at MUX_S0 selects mux_0 to switch B. MUX_S0 is internally pulled high.

Default state for mux_0 is switch A.

MUX_S1

13

A logic low at MUX_S1 selects mux_1 to switch B. MUX_S0 is internally pulled high.

Default state for mux_1 is switch A.

PREL_0

PREL_1

12

1

I

pre-emphasis levels.

PRES_0

PRES_1

36

25

I

Table 4 for switch side pre-emphasis levels.

LB0A

47

I

internally pulled high.

LB0B

48

I

internally pulled high.

LB1A

23

I

internally pulled high.

LB1B

24

I

internally pulled high.

RSV

26

I

Reserve pin to support factory testing. This pin can be left open, or tied to GND, or tied to

GND through an external pull-down resistor.

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