AD9744 datasheet(16/32 Pages) AD

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AD9744

Data Sheet

Rev. C | Page 16 of 32

Figure 29. Clock Termination in PECL Mode

DAC TIMING

Input Clock and Data Timing Relationship

Dynamic performance in a DAC is dependent on the relationship

between the position of the clock edges and the time at which

the input data changes. The AD9744 is rising edge triggered,

and so exhibits dynamic performance sensitivity when the data

transition is close to this edge. In general, the goal when applying

the AD9744 is to make the data transition close to the falling

clock edge. This becomes more important as the sample rate

increases. Figure 30 shows the relationship of SFDR to clock

placement with different sample rates. Note that at the lower

sample rates, more tolerance is allowed in clock placement,

while at higher rates, more care must be taken.

Figure 30. SFDR vs. Clock Placement at fOUT = 20 MHz and 50 MHz

Sleep Mode Operation

The AD9744 has a power-down function that turns off the output

current and reduces the supply current to less than 6 mA over

the specified supply range of 2.7 V to 3.6 V and temperature

range. This mode can be activated by applying a logic level 1 to

the SLEEP pin. The SLEEP pin logic threshold is equal to 0.5 Ω

AVDD. This digital input also contains an active pull-down

circuit that ensures that the AD9744 remains enabled if this

input is left disconnected. The AD9744 takes less than 50 ns to

power down and approximately 5 µs to power back up.

POWER DISSIPATION

The power dissipation, PD, of the AD9744 is dependent on

several factors that include:

•

The power supply voltages (AVDD, CLKVDD, and

DVDD)

•

The full-scale current output IOUTFS

•

The update rate fCLOCK

•

The reconstructed digital input waveform

The power dissipation is directly proportional to the analog supply

current, IAVDD, and the digital supply current, IDVDD. IAVDD is

directly proportional to IOUTFS, as shown in Figure 31, and is

insensitive to fCLOCK. Conversely, IDVDD is dependent on both the

digital input waveform, fCLOCK, and digital supply DVDD. Figure 32

shows IDVDD as a function of full-scale sine wave output ratios

(fOUT/fCLOCK) for various update rates with DVDD = 3.3 V.

Figure 31. IAVDD vs. IOUTFS

Figure 32. IDVDD vs. Ratio at DVDD = 3.3 V

CLK+

TO DAC CORE

CLK–

VTT = 1.3V NOM

Ω

AD9744

CLOCK

RECEIVER

–3

–2

–1

50MHz SFDR

20MHz SFDR

50MHz SFDR

IOUTFS (mA)

RATIO (fOUT/fCLOCK)

0.01

0.1

165MSPS

210MSPS

65MSPS

125MSPS

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