XRT82L24 datasheet(9/43 Pages) EXAR

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XRT82L24

QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. 1.2.3

RDY_DTACK

Ready Output (Data Transfer Acknowledge Output).

With Intel bus timing, RDY is asserted "High" to indicate the device has com-

pleted a read or write operation. When configured in Motorola bus timing,

DTACK is asserted Low to indicate the device has completed a read or write

cycle.

A[3]

A[2]

A[1]

A[0]

Host Mode, Microprocessor Interface Address Bus [3]

Host Mode, Microprocessor Interface Address Bus [2]

Host Mode, Microprocessor Interface Address Bus [1]

Host Mode, Microprocessor Interface Address Bus [0].

D[7]

D[6]

D[5]

D[4]

D[3]

D[2]

D[1]

D[0]

I/O

Data Bus[7:0].

Microprocessor read/write data bus pins.

CLOCKS

MCLK

Master Clock Input.

This signal is an independent 2.048MHz clock with accuracy better than

±50ppm and duty cycle within 40% to 60%. The function of MCLK is to provide

internal timing for the PLL clock recovery circuit, jitter attenuator block, refer-

ence clock during transmit all ones data and timing reference for the micropro-

cessor in Host Mode operation.

If MClk is absent, all receive channels perform as analog front-end (AFE). The

OR-ed RZ data is also available at RxClk output in this mode, instead. The

clock recovery function is disabled.

JITTER ATTENUATOR

TXJA

Transmit Jitter Attenuator Select.

In Hardware Mode, connect this pin “High” to select jitter attenuator in the trans-

mit path and connect Low to disable jitter attenuator.

Setting RXJA simultaneously "High" also disables jitter attenuator selection.

RXJA

Receive Jitter Attenuator Select.

In Hardware Mode, connect this pin “High” to select jitter attenuator in the

receive path and connect Low to disable jitter attenuator.

Setting TXJA simultaneously "High" also disables jitter attenuator selection.

CONTROL

SR/DR

Single rail/Dual Rail Control:

Hardware Mode

Connect this pin “Low” to select transmit and receive data format in dual-rail

mode. In this mode, HDB3 encoder and decoder are not available. Connect this

pin "High" to select single-rail data format.

NOTE: Internally pulled -down with a 50k

Ω resistor.

Codes

Coding/Decoding Select.

In Hardware Mode, if single-rail data format is selected (pin 8 =”1”), connect

this pin "High" to select AMI encoding and decoding. Connect this pin Low to

select HDB3.

PIN DESCRIPTIONS

PIN #NAME

TYPE

DESCRIPTION

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