ESP32C3 datasheet(27/44 Pages) ESPRESSIF

27 / 44 page

Functional Description

During the flash boot process, RWDT and the MWDT in timer group 0 (TIMG0) are enabled automatically in order

to detect and recover from booting errors.

Watchdog timers have the following features:

• four stages, each with a programmable timeout value. Each stage can be configured, enabled and

disabled separately

• interrupt, CPU reset, or core reset for MWDT upon expiry of each stage; interrupt, CPU reset, core reset, or

system reset for RWDT upon expiry of each stage

• 32-bit expiry counter

• write protection, to prevent RWDT and MWDT configuration from being altered inadvertently

• flash boot protection

If the boot process from an SPI flash does not complete within a predetermined period of time, the

watchdog will reboot the entire main system.

3.9 Cryptographic Hardware Accelerators

ESP32-C3 is equipped with hardware accelerators of general algorithms, such as AES-128/AES-256 (FIPS PUB

197), ECB/CBC/OFB/CFB/CTR (NIST SP 800-38A), SHA1/SHA224/SHA256 (FIPS PUB 180-4), and RSA3072.

The chip also supports independent arithmetic, such as Big Integer Multiplication and Big Integer Modular

Multiplication. The maximum operation length for RSA and Big Integer Modular Multiplication is 3072 bits. The

maximum factor length for Big Integer Multiplication is 1536 bits.

3.10

Physical Security Features

• Transparent external flash encryption (AES-XTS algorithm) with software inaccessible key prevents

unauthorized readout of your application code or data.

• Secure boot feature uses a hardware root of trust to ensure only signed firmware (with RSA-PSS signature)

can be booted.

• HMAC module can use a software inaccessible MAC key to generate MAC signatures for identity

verification and other purposes.

• Digital Signature module can use a software inaccessible secure key to generate RSA signatures for identity

verification.

• World Controller provides two running environments for software. All hardware and software resources are

sorted to two groups, and placed in either secure or general world. The secure world cannot be accessed

by hardware in the general world, thus establishing a security boundary.

3.11

Peripheral Pin Configurations

Table 10: Peripheral Pin Configurations

Interface

Signal

Function

ADC

ADC1_CH0

XTAL_32K_P

Two 12-bit SAR ADCs

ADC1_CH1

XTAL_32K_N

ADC1_CH2

GPIO2

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ESP32-C3 Series Datasheet v1.1

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