HT36M4 datasheet(11/23 Pages) HOLTEK

11 / 23 page

HT36M4

Rev. 1.00

August 15, 2005

the other set

-²CLR WDT1² and ²CLR WDT2². Of these

two types of instructions, only one can be active de-

pending on the mask option

-²CLR WDT times selec-

tion option

².Ifthe ²CLR WDT² is selected (i.e. CLRWDT

times equal one), any execution of the

²CLR WDT² in-

struction will clear the WDT. In case

²CLR WDT1² and

²CLR WDT2² are chosen (i.e. CLRWDT times equal

two), these two instructions must be executed to clear

the WDT; otherwise, the WDT may reset the chip due to

time-out.

Power Down Operation

- HALT

The HALT mode is initialized by a HALT instruction and

results in the following:

· The system oscillator will turn off but the WDT oscilla-

tor keeps running (if the WDT oscillator is selected).

Watchdog Timer

- WDT

· The contents of the on-chip RAM and registers remain

unchanged.

· The WDT and WDT prescaler will be cleared and

starts to count again (if the clock comes from the WDT

oscillator).

· All I/O ports maintain their original status.

· The PDF flag is set and the TO flag is cleared.

· The HALT pin will output a high level signal to disable

the external ROM.

The system can leave the HALT mode by means of an

external reset, an interrupt, an external falling edge sig-

nal on port A or a WDT overflow. An external reset

causes a device initialization and the WDT overflow per-

forms a

²warm reset². By examining the TO and PDF

flags, the cause for a chip reset can be determined. The

PDF flag is cleared when there is a system power-up or by

executing the

²CLR WDT² instruction and it is set when a

HALT instruction is executed. The TO flag is set if a WDT

time-out occurs, and causes a wake-up that only resets

the Program Counter and SP, the others remain in their

original status.

The port A wake-up and interrupt methods can be con-

sidered as a continuation of normal execution. Each bit

in port A can be independently selected to wake-up the

device by mask option. Awakening from an I/O port stim-

ulus, the program will resume execution of the next in-

struction. If awakening from an interrupt, two sequences

may occur. If the related interrupts is disabled or the in-

terrupts is enabled but the stack is full, the program will

resume execution at the next instruction. If the interrupt

is enabled and the stack is not full, a regular interrupt re-

sponse takes place.

Once a wake-up event occurs, it takes 1024 tSYS (sys-

tem clock period) to resume to normal operation. In

other words, a dummy cycle period will be inserted after

a wake-up. If the wake-up results from an interrupt ac-

knowledge, the actual interrupt subroutine will be de-

layed by one more cycle. If the wake-up results in next

instruction execution, this will be executed immediately

after a dummy period has finished. If an interrupt re-

quest flag is set to

²1² before entering the HALT mode,

the wake-up function of the related interrupt will be dis-

abled.

To minimize power consumption, all I/O pins should be

carefully managed before entering the HALT status.

Reset

There are three ways in which a reset can occur:

· RES reset during normal operation

· RES reset during HALT

· WDT time-out reset during normal operation

The WDT time-out during HALT is different from other

chip reset conditions, since it can perform a

²warm re -

set

² that resets the Program Counter and SP, leaving

the other circuits in their original state. Some registers

remain unchanged during other reset conditions. Most

registers are reset to the

²initial condition² when the re-

set conditions are met. By examining the PDF and TO

flags, the program can distinguish between different

²chip resets².

t S S T

R E S

V D D

S S T T i m e - o u t

C h i p R e s e t

Reset Timing Chart

R E S

V D D

Reset Circuit

W D T

H A L T

W D T

T i m e - o u t

R e s e t

R E S

C o l d

R e s e t

W a r m R e s e t

P o w e r - o n D e t e c t i n g

S S T

1 0 - s t a g e

R i p p l e C o u n t e r

O S C I

Reset Configuration

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