PCMD3140 datasheet(49/111 Pages) TI

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7.4 Device Functional Modes

7.4.1 Sleep Mode or Software Shutdown

In sleep mode or software shutdown mode, the device consumes very low quiescent current from the AVDD

supply and, at the same time, allows the I2C communication to wake the device for active operation.

The device enters sleep mode when the host device sets the SLEEP_ENZ (P0_R2_D0) bit to 1'b0. If the

SLEEP_ENZ bit is asserted low when the device is in active mode, the device ramps down the volume on

the record data, powers down the analog and digital blocks, and enters sleep mode. However, the device

still continues to retain the last programmed value of the device configuration registers and programmable

coefficients.

In sleep mode, do not perform any I2C transactions, except for exiting sleep mode in order to enter active mode.

After entering sleep mode, wait at least 10 ms before starting I2C transactions to exit sleep mode.

When exiting sleep mode, the host device must configure the PCMD3140-Q1 to use either an external 1.8-V

AREG supply (default setting) or an on-chip, regulator-generated AREG supply. To configure the AREG supply,

write to AREG_SELECT (bit D7) in the same P0_R2 register.

7.4.2 Active Mode

If the host device exits sleep mode by setting the SLEEP_ENZ bit to 1'b1, the device enters active mode. In

active mode, I2C transactions can be done to configure and power-up the device for active operation. After

entering active mode, wait at least 1 ms before starting any I2C transactions to allow the device to complete the

internal wake-up sequence.

Read and write operations to the programmable coefficient registers in page 2, page 3, and page 4 and to the

channel configuration registers (CHx_CFG[1:4]) in page 0 must be done 10 ms after exiting sleep mode.

After configuring all other registers for the target application and system settings, configure the input and

output channel enable registers, IN_CH_EN (P0_R115) and ASI_OUT_CH_EN (P0_R116), respectively. Lastly,

configure the device power-up register, PWR_CFG (P0_R117). All programmable coefficient values must be

written before powering up the respective channel.

In active mode, the power-up and power-down status of various blocks is monitored by reading the read-only

device status bits located in the DEV_STS0 (P0_R117) and DEV_STS1 (P0_R118) registers.

7.4.3 Software Reset

A software reset can be done any time by asserting the SW_RESET (P0_R1_D0) bit, which is a self-clearing

bit. This software reset immediately shuts down the device, and restores all device configuration registers and

programmable coefficients to their default values.

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PCMD3140-Q1

SBASAH3A – APRIL 2022 – REVISED SEPTEMBER 2022

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PCMD3140 Datasheet(PDF) 49 Page - Texas Instruments