PCMD3140 datasheet(7/111 Pages) TI

7 / 111 page

at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, fIN = 1-kHz sinusoidal signal, fS = 48 kHz, PDMCLKx = 64 × fS, 32-bit audio

data, BCLK = 256 × fS, TDM slave mode, and PLL on (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

IOL(I2C)

Low-level digital output

current

SDA, VOL(I2C) = 0.4 V, standard-mode or fast-mode

SDA, VOL(I2C) = 0.4 V, fast-mode plus

IIH

Input logic-high leakage for

digital inputs

All digital pins except PDMDIN1_GPI1, PDMDIN2_GPI2

pins,

input = IOVDD

–5

0.1

µA

IIL

Input logic-low leakage for

digital inputs

All digital pins except PDMDIN1_GPI1, PDMDIN2_GPI2

pins,

input = 0 V

–5

0.1

µA

VIL(GPIx)

Low-level digital input logic

voltage threshold

PDMDIN1_GPI1, PDMDIN2_GPI2 digital pins, AVDD

1.8-V operation

–0.3

0.35 × AVDD

PDMDIN1_GPI1, PDMDIN2_GPI2 digital pins, AVDD

3.3-V operation

–0.3

0.8

VIH(GPIx)

High-level digital input logic

voltage threshold

PDMDIN1_GPI1, PDMDIN2_GPI2 digital pins, AVDD

1.8-V operation

0.65 × AVDD

AVDD + 0.3

PDMDIN1_GPI1, PDMDIN2_GPI2 digital pins, AVDD

3.3-V operation

AVDD + 0.3

VOL(GPOx)

Low-level digital output

voltage

PDMDIN1_GPI1, PDMDIN2_GPI2 digital pins, IOL = –2

mA, AVDD 1.8-V operation

0.45

PDMDIN1_GPI1, PDMDIN2_GPI2 digital pins, IOL = –2

mA, AVDD 3.3-V operation

0.4

VOH(GPOx)

High-level digital output

voltage

PDMDIN1_GPI1, PDMDIN2_GPI2 digital pins, IOH = 2

mA, AVDD 1.8-V operation

AVDD – 0.45

PDMDIN1_GPI1, PDMDIN2_GPI2 digital pins, IOH = 2

mA, AVDD 3.3-V operation

2.4

IIH(GPIx)

Input logic-high leakage for

digital inputs

PDMDIN1_GPI1, PDMDIN2_GPI2 digital pins, input =

AVDD

–5

0.1

µA

IIL(GPIx)

Input logic-high leakage for

digital inputs

PDMDIN1_GPI1, PDMDIN2_GPI2 digital pins, input = 0

–5

0.1

µA

CIN

Input capacitance for digital

inputs

All digital pins

RPD

Pulldown resistance for

digital I/O pins when

asserted on

kΩ

TYPICAL SUPPLY CURRENT CONSUMPTION

IAVDD

Current consumption in

sleep mode (software

shutdown mode)

All external clocks stopped, AVDD = 3.3 V

µA

IAVDD

All external clocks stopped, AVDD = 1.8 V, external

AREG supply (AREG shorted to AVDD)

IIOVDD

All external clocks stopped, IOVDD = 3.3 V

0.5

IIOVDD

All external clocks stopped, IOVDD = 1.8 V

0.3

IAVDD

Current consumption with

4-channel PDM input

recording

AVDD = 3.3 V

9.1

IAVDD

AVDD = 1.8 V, external AREG supply (AREG shorted to

AVDD)

8.1

IIOVDD

IOVDD = 3.3 V

0.1

IIOVDD

IOVDD = 1.8 V

0.05

IAVDD

Current consumption with

4-channel PDM input

recording, fS = 16 kHz,

PDMCLKx = 96 × fS, PLL

on and BCLK = 384 × fS

AVDD = 3.3 V

7.3

IAVDD

AVDD = 1.8 V, external AREG supply (AREG shorted to

AVDD)

6.3

IIOVDD

IOVDD = 3.3 V

0.1

IIOVDD

IOVDD = 1.8 V

0.05

(1)

Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with no signal, measured A-weighted over a 20-Hz to

20-kHz bandwidth using an audio analyzer.

(2)

All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may

result in higher THD and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter

removes out-of-band noise, which, although not audible, may affect dynamic specification values.

(3)

The device performance parameters, SNR, DR and THD+N, are mainly limited by single-bit PDM modulator generated data output.

The THD+N peformance for single-bit PDM modulator output itself is generally not so good for signal above –10-dB full-scale.

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PCMD3140-Q1

SBASAH3A – APRIL 2022 – REVISED SEPTEMBER 2022

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