ICS94235

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Pin Descriptions

PIN NU MBER

PIN NA ME

TYPE

D ESCR IPTION

1

RESET#

OUT

Real time system reset signal for frequency value or w atchdog timmer

timeout. This signal is active low.

2

PD#

1

IN

As ynchronous active low input pin used to pow er dow n the device into a low

power state. The internal clocks are disabled and the VCO and the crystal are

stopped. The latency of the pow er dow n w ill not be greater than 3ms.

4

X 1

IN

Crystal input,nominally 14.318M H z.

5

X 2

OU T

Crystal output, nominally 14.318M H z.

3, 11, 16, 23, 29,

34, 41, 48

G ND

PWR

Ground pins

8, 17, 28, 35, 40

V DD

PWR

Pow er supply pins, nominal 3.3V

6

A VD D

PWR

A nalog pow er supply pin, nominal 3.3V

FS0

2, 3

IN

Frequency select pin.

REF0

OU T

14.318 M H z reference clock.

FS1

2, 3

IN

Frequency select pin.

A GP0

OU T

AG P outputs defined as 2X PCI. These may not be stopped.

10

A GP1

OU T

AG P outputs defined as 2X PCI. These may not be stopped.

PCICLK _F

OU T

Free running PCICLK not stoped by PCI_STO P#

FS2

1, 3

IN

Frequency select pin.

20, 19, 15, 14, 13

PCICLK

(5:4) (2:0)

OU T

PCI clock outputs.

PCICLK 3

OU T

PCI clock output.

M O DE

1, 3

IN

Function select pin, 1=D es ktop M ode, 0=M obile M ode.

21

AV DD 48

PWR

A nalog pow er s upply pin, nominal 3.3V

FS3

2, 3

IN

Frequency select pin.

48M Hz

OU T

48M H z output clock

24

SCLK

IN

Clock input of I

2

C input, 5V tolerant input

PCI_STO P#

1

IN

Stops all PCICLK s besides the PCICLK _F clocks at logic 0 level,

when input low

SD RAM 10

OU T

SD RA M clock output.

25, 26, 30, 31, 32,

33, 36, 37, 38, 39,

42, 43

SD RAM

(12:11, 9:0 )

OU T

SD RA M clock outputs.

44

SD ATA

I/O

Data pin for I

2

C circuitry 5V tolerant

45, 47

CPU CLK T (1:0)

OUT

"True" clocks of differential pair CPU outputs. These open drain outputs

need an external 1.5V pull-up.

46

CPU CLK C0

OU T

"Complementory" clocks of differential pair CPU outputs. This open drain

output need an external 1.5V pull-up.

9

7

27

12

22

18