STA1275 datasheet(98/109 Pages) STMICROELECTRONICS

98 / 109 page

Electrical characteristics

STA1295, STA1275

98/109

DS12586 Rev 5

4.14.4

LCD interface timing

The following tables provide the timings for LCD interface.

The launching edge is programmable: the edge should be chosen in such a way that

capturing occurs on the clock edge opposite to the launching edge.

Timings are provided taking the active edge at SoC side as reference.

4.14.5

VIP interface timing

The following table provides the timings for VIP interface.

Table 60. SQIO

Type

Symbol

Min Max Unit Load

Notes

Clock

CLK freq

—

125 MHz 25 pF

—

CLK period

—

25 pF

CLK duty cycle

—

Input

TIS

—

TIH

—

Output Todly

-1

25 pF

Table 61. LCD - Single display

Type

Symbol

Min

Max Unit

Load

Notes

Clock

Display CLK freq

—

156

MHz 25 pF

—

Display CLK period

6.41

—

25 pF

Display CLK duty cycle

—

Pixel CLK freq

—

156

MHz 25 pF

Pixel CLK period

6.41

—

25 pF

Pixel CLK duty cycle

—

Output Todly

-0.72

25 pF

Table 62. LCD - Dual display with edge shift (valid for each display output)

Type

Symbol

Min

Max

Unit

Load

Notes

Clock

Display CLK freq

—

44.55 MHz 25 pF

—

Display CLK period

22.45

—

25 pF

Display CLK duty cycle

—

Pixel CLK freq

—

89.1

MHz 25 pF

Pixel CLK period

11.22

—

25 pF

Pixel CLK duty cycle

—

Output Todly

-2.5

3.5

25 pF

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