STA1275 datasheet(19/109 Pages) STMICROELECTRONICS

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DS12586 Rev 5

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STA1295, STA1275

System description

106

intensive tasks to offload main CPU. The secure subsystem communicates with the

application running on Cortex® A7 using a Hardware Mailbox interrupt based mechanism.

2.15

Crypto accelerator engine

In order to efficiently support security, STA1275 and STA1295 embed a dedicated, flexible

hardware accelerator for the following set of cryptographic operations:

•

DES, TripleDES

•

AES 128, 192, 256:

Modes of operation: ECB, CBC, CTR, XTS, CCM, GCM, CFB, OFB, CMAC

•

SHA1, SHA256, SHA384, SHA512 with HMAC

•

Public Key Accelerator for RSA, DH, Elliptic Curve Cryptography

•

TRNG, for random number generation, compliant with NIST SP800-90B

These cryptographic acceleration features, along with the embedded secure OTP, the

TrustZone aware bus infrastructure, and secure ROM boot, provide a complete set of

components to build a secure system, for data confidentiality, integrity, as well as code

integrity and rollback protection.

2.16

General purpose ADC

The system is equipped with 10-inputs SAR ADC with a resolution of 10-bits and sampling

frequency up to 2.5 MHz. In addition, a second instance of the same SAR ADC implements

a continuous voltage monitoring on 6 more channels, to support DC offset detection feature

in hardware.

2.17

GPIOs

STA1275 and STA1295 have a total of 160 GPIOs, which can be independently configured

either as INPUT or OUTPUT. In order to make the system flexible, these IOs are multiplexed

on PINs with other peripherals. Alternate function scheme is described in Table 10.

GPIOs are divided into 3 sets:

•

128 application GPIOs:

Most of system digital IOs are exposed as alternate functions of application GPIOs.

This allows maximum flexibility in system definition.

•

16 secure GPIOs (s_GPIO):

This set of GPIOs can be selectively configured as secure, in order to securely control

IO functionality, for secure blocks which expose an interface.

•

16 M3_GPIOs:

This set of IOs is dedicated to the Cortex® M3 microcontroller and its peripherals.

2.17.1

Application GPIO alternate function mapping

Note:

All GPIOs pins are configured by default at reset in GPIO input mode. As an exception to

this general rule, the reset default state of GPIO108 to GPIO113 depends on the value

latched at reset of REMAP[1:0] (Refer to Table 10 footnote (1)).

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