STA1275 datasheet(10/109 Pages) STMICROELECTRONICS

10 / 109 page

System description

STA1295, STA1275

10/109

DS12586 Rev 5

•

Vertex DMA streams

With a performance of up to:

•

Vertex rate: 120 MVtx/sec

•

Pixel Rate: 240 MPix/sec

2.8.1

Unified shader features

2.8.2

Vertex processing features

Table 1. Unified shader features

Features

GPU support

Shader type and execution units

Unified shader, SIMD4, SFP32 Trans

Swizzle capabilities

Full 32-bit word level swizzle in a 128-bit vector

GPR's per shader core

Up to 512 general purpose registers, 128 bits each

Uniform registers

Uniform total: 320 registers

Vertex Shader: 128 registers, 128 bits each

Fragment Shader: 128 registers, 128 bits each

FP denorm and rounding options

Denorms are set to zero. Supports rounding to zero.

Maximum number of data input attributes

Maximum of 12 vertex shader input elements

Maximum of 8 fragment shader input elements

Sampler Count

Total: 12 (4 VS Samplers, 8 PS Samplers)

Maximum number of instructions

256

Maximum number of vertex streams

Maximum number of threads in flight per

shader core

Subroutines

4 levels

Conditional branch support

GT, LT, EQ, GE, LE, NE

Shader instruction rate

1-cycle throughput for all shader instructions

Floating-point instruction precision

SIMD4 (vector): 23.5 bits

Fragment shader video

Supports video texture

Table 2. Vertex processing features

Features

GPU support

Vx D3D, OGL ES formats supported

BYTE, UBYTE, SHORT, USHORT, INT, UINT, DEC,

UDEC, FLOAT, FLOAT16, D3DCOLOR,

FIXED16DOT16

Vertex data size limits

256 bytes

Pre shader cache

1 kB

Post shader cache

8 vertices

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