Integrated

Circuit

Systems, Inc.

ICS951402

Advance Information

0660—05/05/05

Block Diagram

Pin Configuration

Recommended Application:

ATI chipset, P4 system, Banias system

Output Features:

•

2 - Pairs of differential CPUCLKs (differential current mode)

•

1 - SDRAM @ 3.3V

•

8 - PCI @3.3V (selectable 33/66 MHz) (2 free-running)

•

2 - AGP @ 3.3V

•

2- 48MHz, @3.3V fixed.

•

1- 24/48MHz, @3.3V selectable by I

(Default is 24MHz)

•

3- REF @3.3V, 14.318MHz.

Features/Benefits:

•

Support for Intel Banias power management features

•

Programmable output frequency, divider ratios, output rise/

falltime, output skew.

•

Programmable spread percentage for EMI control.

•

Watchdog timer technology to reset system

if system malfunctions.

•

Programmable watch dog safe frequency.

•

Support I

operations.

•

Supports spread spectrum for EMI reduction; default is

spread spectrum ON.

Programmable Timing Control Hub™ for P4™ processor

* These inputs have a 120K pull up to VDD.

** These inputs have a 120K pull down to GND.

ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.

ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.

48-Pin TSSOP & SSOP

Power Groups

VDDCPU = CPU

VDDPCI = PCICLK_F, PCICLK

VDDSD = SDRAM

AVDD48 = 48MHz, 24MHz, fixed PLL

AVDD = Analog Core PLL

VDDAGP= AGP

VDDREF = Xtal, REF

Skew Requirements

VDDREF 1

48 VDDSDR

FS0/REF0 2

47 SDRAM_OUT

FS1/REF1 3

46 GNDSDR

FS2/REF2 4

45 CPU_STOP#*

GNDREF 5

44 CPUCLKT1

X1 6

43 CPUCLKC1

X2 7

42 VDDCPU

GND 8

41 GNDCPU

VDD 9

40 CPUCLKT0

*VttPWR_GD/PD# 10

39 CPUCLKC0

PCI66/33#_SEL 11

38 IREF

PCI_STOP#* 12

37 GND

VDDPCI 13

36 AVDD

FS3/PCICLK_F0 14

35 SCLK

FS4/PCICLK_F1 15

34 SDATA

PCICLK016

33GNDAGP

PCICLK117

32AGPCLK0

GNDPCI 18

31 AGPCLK1

VDDPCI 19

30 VDDAGP

PCICLK220

29AVDD48

PCICLK321

2848MHz_0

PCICLK422

2748MHz_1

PCICLK5 23

26 24_48MHz/SEL24_48#MHz**

GNDPCI 24

25 GND48

PCI-PCI

<±350ps

AGP-AGP

<±350ps

CPU-AGP

<±500ps

CPU-PCI

<±500ps

CPU-SDRAM

<±1ns

AGP-PCI

AGP leading

<±1ns

I REF

CPU

DIVDER

PLL2

PLL1

Spread

Spectrum

48MHz (0:1)

24_48MHz

PCICLK (5:0)

AGP (1:0)

PCICLK_F (1:0)

2

2

1

6

3

X1

X2

XTAL

OSC

SDRAM

SDRAM_OUT

PCI

DIVDER

Stop

SDATA

SCLK

FS (4:0)

PD#

PCI_STOP#

CPU_STOP#

PD#/Vtt_PWRGD

PCI66/33#SEL

24_48SEL#

Control

Logic

Config.

Reg.

/ 2

REF (2:0)

AGP

DIVDER

Stop

2

2

CPUCLKT (1:0)

CPUCLKC (1:0)