LM4982 datasheet(15/21 Pages) NSC

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Application Information (Continued)

HP SENSE FUNCTION

Connecting headphones to the headphone jack disconnects

the headphone jack contact pin from OUT_L and allows Rpu

to pull the HP Sense pin up to V

DD. This enables the device.

A microprocessor or a switch can replace the headphone

jack contact pin.

Shutdown

(Bit CD0)

HPS pin

Operational Mode

Logic High

Logic Low

Standby Mode

Logic High

Full Power Mode

Logic Low

Micro-Power Shutdown

Logic Low

Logic High

Micro-Power Shutdown

INTELLISENSE

National’s Intellisense technology allows the LM4982 to de-

tect whether a mono or stereo headphone has been inster-

ted in to the headphone jack. If a mono headphone is

inserted into a device that is designed for a stereo head-

phone, one of the amplifiers will be shorted to ground. With-

out Intellisense, this may damage the device or, best case,

the device will draw excessive current, shortening battery

life.

Intellisense works by first waiting for one of the following

events:

• When the device powers up, if a headphone is already

inserted

• When a headphone is inserted, if the device is already

powered up

• After the thermal shutdown circuitry is activated.

The occurrence of one of these events triggers the Intel-

lisense circuitry to apply a small voltage on both left and right

outputs and sense the resulting current through the load. If

the load connected to the amplifier is greater than 9

Ω, the

amplifier driving it will be in full power mode. If the load is

less than 3

Ω, the LM4982 will assume a short to ground and

shutdown the driving amplifier. Intellisense puts the LM4982

in mono mode when the right channel is shorted. For extra

protection both amplifiers will be shutdown when the left

channel is shorted to ground. The Intellisense feature can be

enabled and disabled through an I2C command.

This Intellisense feature is designed for headphones with a

nominal impedance of 16

Ω or greater, using lower imped-

ance loads may cause this feature to operate incorrectly.

MONO/STEREO OPERATION

When Intellisense is disabled the value of the CD1 bit of the

mode control determines if the LM4982 is in mono or stereo

mode. When the LM4982 is in mono mode the left and right

input signals are mixed to the left channel amplifier and

attenuated by -6dB. The right channel amplifier is put in

shutdown to save power. The mixing function allows full

reproduction of a stereo input signal in a mono headphone

and optimum headroom is kept by attenuating by a factor of

two.

2C COMPATIBLE INTERFACE

The LM4982 uses a serial bus, which conforms to the I

protocol, to control the chip’s functions with two wires: clock

(SCL) and data (SDA). The clock line is uni-directional. The

data line is bi-directional (open-collector). The maximum

clock frequency specified by the I

2C standard is 400kHz. In

this discussion, the master is the controlling microcontroller

and the slave is the LM4982.

The bus format for the I

2C interface is shown in Figure 2. The

bus format diagram is broken up into six major sections:

The "start" signal is generated by lowering the data signal

while the clock signal is high. The start signal will alert all

devices attached to the I

2C bus to check the incoming ad-

dress against their own address.

The 8-bit chip address is sent next, most significant bit first.

The data is latched in on the rising edge of the clock. Each

address bit must be stable while the clock level is high.

After the last bit of the address bit is sent, the master

releases the data line high (through a pull-up resistor). Then

the master sends an acknowledge clock pulse. If the

LM4982 has received the address correctly, then it holds the

data line low during the clock pulse. If the data line is not

held low during the acknowledge clock pulse, then the mas-

ter should abort the rest of the data transfer to the LM4982.

The 8 bits of data are sent next, most significant bit first.

Each data bit should be valid while the clock level is stable

high.

After the data byte is sent, the master must check for another

acknowledge to see if the LM4982 received the data.

If the master has more data bytes to send to the LM4982,

then the master can repeat the previous two steps until all

data bytes have been sent.

The "stop" signal ends the transfer. To signal "stop", the data

signal goes high while the clock signal is high. The data line

should be held high when not in use.

201614A1

FIGURE 4.

20161460

FIGURE 5.

LM4982 Datasheet(PDF) 15 Page - National Semiconductor (TI)

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