ADC14155EB datasheet(17/19 Pages) NSC

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Applications Information (Continued)

analog circuitry, degrading dynamic performance. Adequate

bypassing, limiting output capacitance and careful attention

to the ground plane will reduce this problem. Additionally,

bus capacitance beyond the specified 5 pF/pin will cause t

to increase, reducing the setup and hold time of the ADC

output data. The result could be an apparent reduction in

dynamic performance.

To minimize noise due to output switching, minimize the load

currents at the digital outputs. This can be done by connect-

ing

1.8V

3.3V

level

translator

such

the

SN74AVCA164245 between the ADC outputs and any other

circuitry. Only one load should be connected to each output

pin. Additionally, inserting series resistors of about 22

Ω at

the digital outputs, close to the ADC pins, will isolate the

outputs from trace and other circuit capacitances and limit

the output currents, which could otherwise result in perfor-

mance degradation. See Figure 4.

5.0 POWER SUPPLY CONSIDERATIONS

The power supply pins should be bypassed with a 0.1 µF

capacitor and with a 100 pF ceramic chip capacitor close to

each power pin. Leadless chip capacitors are preferred be-

cause they have low series inductance.

As is the case with all high-speed converters, the ADC14155

is sensitive to power supply noise. Accordingly, the noise on

the analog supply pin should be kept below 100 mV

P-P.

No pin should ever have a voltage on it that is in excess of

the supply voltages, not even on a transient basis. Be espe-

cially careful of this during power turn on and turn off.

The V

DR pin provides power for the output drivers and may

be operated from a supply in the range of 1.6V to 2.0V. This

enables lower power operation, reduces the noise coupling

effects from the digital outputs to the analog circuitry and

simplifies interfacing to lower voltage devices and systems.

Note, however, that t

OD increases with reduced VDR. Also

note that a level translator may be required.

6.0 LAYOUT AND GROUNDING

Proper grounding and proper routing of all signals are es-

sential to ensure accurate conversion. Maintaining separate

analog and digital areas of the board, with the ADC14155

between these areas, is required to achieve specified per-

formance.

The ground return for the data outputs (DRGND) carries the

ground current for the output drivers. The output current can

exhibit high transients that could add noise to the conversion

process. To prevent this from happening, the DRGND pins

should NOT be connected to system ground in close prox-

imity to any of the ADC14155’s other ground pins.

Capacitive coupling between the typically noisy digital cir-

cuitry and the sensitive analog circuitry can lead to poor

performance. The solution is to keep the analog circuitry

separated from the digital circuitry, and to keep the clock line

as short as possible.

The effects of the noise generated from the ADC output

switching can be minimized through the use of 22

Ω resistors

in series with each data output line. Locate these resistors as

close to the ADC output pins as possible.

Since digital switching transients are composed largely of

high frequency components, total ground plane copper

20179013

FIGURE 4. Application Circuit using Transformer Drive Circuit

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