ADC14155EB datasheet(14/19 Pages) NSC

14 / 19 page

Functional Description

Operating on dual +3.3V and +1.8V supplies, the ADC14155

digitizes a differential analog input signal to 14 bits, using a

differential pipelined architecture with error correction cir-

cuitry and an on-chip sample-and-hold circuit to ensure

maximum performance.

The user has the choice of using an internal 1.0V stable

reference, or using an external reference. The ADC14155

will accept an external reference between 0.8V and 1.2V

(1.0V recommended) which is buffered on-chip to ease the

task of driving that pin. The +1.8V output driver supply

reduces power consumption and decreases the noise at the

output of the converter.

The quad state function pin CLK_SEL/DF (pin 8) allows the

user to choose between using a single-ended or a differen-

tial clock input and between offset binary or 2’s complement

output data format. The digital outputs are CMOS compatible

signals that are clocked by a synchronous data ready output

signal (DRDY, pin 34) at the same rate as the clock input. For

the ADC14155 the clock frequency can be between 5 MSPS

and 155 MSPS (typical) with fully specified performance at

155 MSPS. The analog input is acquired at the falling edge

of the clock and the digital data for a given sample is output

on the falling edge of the DRDY signal and is delayed by the

pipeline for 8 clock cycles. The data should be captured on

the rising edge of the DRDY signal.

Power-down is selectable using the PD pin (pin 7). A logic

high on the PD pin disables everything except the voltage

reference circuitry and reduces the converter power con-

sumption to 5 mW with no clock running. For normal opera-

tion, the PD pin should be connected to the analog ground

(AGND). A duty cycle stabilizer maintains performance over

a wide range of clock duty cycles.

Applications Information

1.0 OPERATING CONDITIONS

We recommend that the following conditions be observed for

operation of the ADC14155:

3.0V

≤ V

≤ 3.6V

D =VA

DR = 1.8V

5 MHz

≤ f

CLK

≤ 155 MHz

1.0V internal reference

0.9V

≤ V

REF

≤ 1.1V (for an external reference)

CM = 1.5V (from VRM)

2.0 ANALOG INPUTS

2.1 Signal Inputs

2.1.1 Differential Analog Input Pins

The ADC14155 has one pair of analog signal input pins,

IN+ and VIN−, which form a differential input pair. The input

signal, V

IN, is defined as

IN =(VIN+) – (VIN−)

Figure 2 shows the expected input signal range. Note that

the common mode input voltage, V

CM, should be 1.5V. Using

RM (pin 45) for VCM will ensure the proper input common

mode level for the analog input signal. The peaks of the

individual input signals should each never exceed 2.6V.

Each analog input pin of the differential pair should have a

peak-to-peak voltage equal to the reference voltage, V

REF,

be 180˚ out of phase with each other and be centered

around V

CM.The peak-to-peak voltage swing at each analog

input pin should not exceed the value of the reference volt-

age or the output data will be clipped.

For single frequency sine waves the full scale error in LSB

can be described as approximately

FS = 16384(1-sin (90˚ + dev))

Where dev is the angular difference in degrees between the

two signals having a 180˚ relative phase relationship to each

other (see Figure 3). For single frequency inputs, angular

errors result in a reduction of the effective full scale input. For

complex waveforms, however, angular errors will result in

distortion.

It is recommended to drive the analog inputs with a source

impedance less than 100

Ω. Matching the source impedance

for the differential inputs will improve even ordered harmonic

performance (particularly second harmonic).

Table 1 indicates the input to output relationship of the

ADC14155.

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FIGURE 2. Expected Input Signal Range

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FIGURE 3. Angular Errors Between the Two Input

Signals Will Reduce the Output Level or Cause

Distortion

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