ADC14155EB datasheet(15/19 Pages) NSC

15 / 19 page

Applications Information (Continued)

TABLE 1. Input to Output Relationship

IN+

IN−

Binary Output

2’s Complement Output

CM −VREF/2

CM +VREF/2

00 0000 0000 0000

10 0000 0000 0000

Negative Full-Scale

CM −VREF/4

CM +VREF/4

01 0000 0000 0000

11 0000 0000 0000

10 0000 0000 0000

00 0000 0000 0000

Mid-Scale

CM +VREF/4

CM −VREF/4

11 0000 0000 0000

01 0000 0000 0000

CM +VREF/2

CM −VREF/2

11 1111 1111 1111

01 1111 1111 1111

Positive Full-Scale

2.1.2 Driving the Analog Inputs

The V

IN+ and the VIN− inputs of the ADC14155 have an

internal sample-and-hold circuit which consists of an analog

switch followed by a switched-capacitor amplifier. The ana-

log inputs are connected to the sampling capacitors through

NMOS switches, and each analog input has parasitic capaci-

tances associated with it.

When the clock is high, the converter is in the sample phase.

The analog inputs are connected to the sampling capacitor

through the NMOS switches, which causes the capacitance

at the analog input pins to appear as the pin capacitance

plus the internal sample and hold circuit capacitance (ap-

proximately 9 pF). While the clock level remains high, the

sampling capacitor will track the changing analog input volt-

age. When the clock transitions from high to low, the con-

verter enters the hold phase, during which the analog inputs

are disconnected from the sampling capacitor. The last volt-

age that appeared at the analog input before the clock

transition will be held on the sampling capacitor and will be

sent to the ADC core. The capacitance seen at the analog

input during the hold phase appears as the sum of the pin

capacitance and the parasitic capacitances associated with

the sample and hold circuit of each analog input (approxi-

mately 6 pF). Once the clock signal transitions from low to

high, the analog inputs will be reconnected to the sampling

capacitor to capture the next sample. Usually, there will be a

difference between the held voltage on the sampling capaci-

tor and the new voltage at the analog input. This will cause a

charging glitch that is proportional to the voltage difference

between the two samples to appear at the analog input pin.

The input circuitry must be fast enough to allow the sampling

capacitor to fully charge before the clock signal goes high

again, as incomplete settling can degrade the SFDR perfor-

mance.

A single-ended to differential conversion circuit is shown in

Figure 4. A transformer is preferred for high frequency input

signals. Terminating the transformer on the secondary side

provides two advantages. First, it presents a real broadband

impedance to the ADC inputs and second, it provides a

common path for the charging glitches from each side of the

differential sample-and-hold circuit.

One short-coming of using a transformer to achieve the

single-ended to differential conversion is that most RF trans-

formers have poor low frequency performance. A differential

amplifier can be used to drive the analog inputs for low

frequency applications. The amplifier must be fast enough to

settle from the charging glitches on the analog input resulting

from the sample-and-hold operation before the clock goes

high and the sample is passed to the ADC core.

The SFDR performance of the converter depends on the

external signal conditioning circuity used, as this affects how

quickly the sample-and-hold charging glitch will settle. An

external resistor and capacitor network as shown in Figure 4

should be used to isolate the charging glitches at the ADC

input from the external driving circuit and to filter the wide-

band noise at the converter input. These components should

be placed close to the ADC inputs because the analog input

of the ADC is the most sensitive part of the system, and this

is the last opportunity to filter that input. For Nyquist appli-

cations the RC pole should be at the ADC sample rate. The

ADC input capacitance in the sample mode should be con-

sidered when setting the RC pole. For wideband undersam-

pling applications, the RC pole should be set at about 1.5 to

2 times the maximum input frequency to maintain a linear

delay response.

2.1.3 Input Common Mode Voltage

The input common mode voltage, V

CM, should be in the

range of 1.4V to 1.6V and be a value such that the peak

excursions of the analog signal do not go more negative than

ground or more positive than 2.6V. It is recommended to use

RM (pin 45) as the input common mode voltage.

2.2 Reference Pins

The ADC14155 is designed to operate with an internal 1.0V

reference, or an external 1.0V reference, but performs well

with external reference voltages in the range of 0.8V to 1.2V.

The internal 1.0 Volt reference is the default condition when

no external reference input is applied to the V

REF pin. If a

voltage in the range of 0.8V to 1.2V is applied to the V

REF

pin, then that voltage is used for the reference. The V

REF pin

should always be bypassed to ground with a 0.1 µF capaci-

tor close to the reference input pin. Lower reference voltages

will decrease the signal-to-noise ratio (SNR) of the

ADC14155. Increasing the reference voltage (and the input

signal swing) beyond 1.2V may degrade THD for a full-scale

input, especially at higher input frequencies.

It is important that all grounds associated with the reference

voltage and the analog input signal make connection to the

ground plane at a single, quiet point to minimize the effects

of noise currents in the ground path.

The Reference Bypass Pins (V

RP,VRM, and VRN) are made

available for bypass purposes. All these pins should each be

bypassed to ground with a 0.1 µF capacitor. A 0.1 µF and a

10 µF capacitor should be placed between the V

RP and VRN

pins, as shown in Figure 4. This configuration is necessary to

avoid reference oscillation, which could result in reduced

SFDR and/or SNR. V

RM may be loaded to 1mA for use as a

temperature stable 1.5V reference. The remaining pins

should not be loaded.

Smaller capacitor values than those specified will allow

faster recovery from the power down mode, but may result in

degraded noise performance. Loading any of these pins,

other than V

RM, may result in performance degradation.

The nominal voltages for the reference bypass pins are as

follows:

RM = 1.5 V

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