ADC14155EB datasheet(5/19 Pages) NSC

5 / 19 page

Pin Descriptions and Equivalent Circuits (Continued)

Pin No.

Symbol

Equivalent Circuit

Description

CLK_SEL/DF

This is a four-state pin controlling the input clock mode and

output data format.

CLK_SEL/DF = V

A, CLK+ and CLK− are configured as a

differential clock input. The output data format is 2’s

complement.

CLK_SEL/DF = (2/3)*V

A, CLK+ and CLK− are configured as a

differential clock input. The output data format is offset binary.

CLK_SEL/DF = (1/3)*V

A, CLK+ is configured as a single-ended

clock input and CLK− should be tied to AGND. The output data

format is 2’s complement.

CLK_SEL/DF = AGND, CLK+ is configured as a single-ended

clock input and CLK− should be tied to AGND. The output data

format is offset binary.

7PD

This is a two-state input controlling Power Down.

PD=V

A, Power Down is enabled. In the Power Down state

only the reference voltage circuitry remains active and power

dissipation is reduced.

PD = AGND, Normal operation.

17-24,

27-32

D0–D13

Digital data output pins that make up the 14-bit conversion

result. D0 (pin 17) is the LSB, while D13 (pin 32) is the MSB of

the output word. Output levels are CMOS compatible.

OVR

Over-Range Indicator. This output is set HIGH when a sample

amplitude exceeds the 14-bit conversion range (0 to 16383).

DRDY

Data Ready Strobe. This pin is used to clock the output data. It

has the same frequency as the sampling clock. One word of

data is output in each cycle of this signal. The rising edge of

this signal should be used to capture the output data.

ANALOG POWER

1, 6, 9, 37,

40, 41, 48

Positive analog supply pins. These pins should be connected

to a quiet +3.3V source and be bypassed to AGND with 100

pF and 0.1 µF capacitors located close to the power pins.

2, 5, 10, 38,

39, 42, 47

AGND

The ground return for the analog supply.

DIGITAL POWER

Positive digital supply pin. This pin should be connected to a

quiet +3.3V source and be bypassed to DGND with a 100 pF

and 0.1 µF capacitor located close to the power pin.

DGND

The ground return for the digital supply.

15, 25, 36

Positive driver supply pin for the ADC14155’s output drivers.

This pin should be connected to a quiet voltage source of

+1.8V and be bypassed to DRGND with 100 pF and 0.1 µF

capacitors located close to the power pins.

16, 26, 35

DRGND

The ground return for the digital output driver supply. These

pins should be connected to the system digital ground, but not

be connected in close proximity to the ADC’s DGND or AGND

pins. See Section 6.0 (Layout and Grounding) for more details.

ADC14155EB Datasheet(PDF) 5 Page - National Semiconductor (TI)

ADC14155EB Datasheet(HTML) 5 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

Datasheet Download

Link URL