GL3523 Datasheet

© 2017 Genesys Logic, Inc. - All rights reserved.

Page 4

GLI Confidential

Table of Contents

CHAPTER 1

GENERAL DESCRIPTION......................................................................... 8

CHAPTER 2

FEATURES .................................................................................................... 8

CHAPTER 3

PIN ASSIGNMENT..................................................................................... 11

3.1 GL3523 Pin-out Diagram............................................................................................ 11

3.2 GL3523 Pin Descriptions ............................................................................................ 14

3.3 GL3523-S Series Pin-out Diagram............................................................................. 17

3.4 GL3523-S Pin Descriptions......................................................................................... 22

CHAPTER 4

FUNCTION DESCRIPTION ..................................................................... 26

4.1 GL3523 Functional Block ........................................................................................... 26

4.2 GL3523-S Functional Block........................................................................................ 27

4.3 General Description..................................................................................................... 28

4.3.1 USB 2.0 USPORT Transceiver ........................................................................... 28

4.3.2 USB 3.1 Gen 1 USPORT Transceiver................................................................ 28

4.3.3 PLL (Phase Lock Loop) ...................................................................................... 28

4.3.4 Regulator .............................................................................................................. 28

4.3.5 SPI Engine ............................................................................................................ 28

4.3.6 RAM/ROM/CPU.................................................................................................. 28

4.3.7 UTMI (USB 2.0 Transceiver Microcell Interface)............................................ 28

4.3.8 SIE (Serial Interface Engine).............................................................................. 28

4.3.9 Control/Status Register ....................................................................................... 28

4.3.10 Power Management Engine .............................................................................. 28

4.3.11 Router/Aggregator Engine................................................................................ 29

4.3.12 REPEATER ....................................................................................................... 29

4.3.13 TT ........................................................................................................................ 29

4.3.14 CDP Control Logic ............................................................................................ 30

4.3.15 USB 3.1 Gen 1/USB 2.0 DSPORT Transceiver ............................................... 30

4.4 Configuration and I/O Settings .................................................................................. 31

4.4.1 RESET Setting ..................................................................................................... 31

4.4.2 PGANG Setting.................................................................................................... 32