Preload and Observability of Registers

The ATV5000’s registers include circuity to load and unload

them serially. This feature simplifies testing. Any state can be

forced into the registers to control test sequencing, and all regis-

will force it low, independent of the polarity or other configura-

tion bit settings.

The preload/observe state is entered by placing an 11-V to 14-V

signal on pin 68 on the JLCC. When the clock (pin 1) is pulsed

high, data (pin 2) is clocked serially through all registers in the

device, as in the following table. All register contents are also

clocked out of the device on Pin 65 in FIFO fashion. If ob-

servability only is required, data out should be connected back

to data in. If preload only is required, OE (pin 66) can be held

high and data out (pin 65) will remain high impedance.

Any user contemplating the use of register preload/obervability

is encouraged to contact Atmel’s PLD applications department.

Note: All register clock terms or pins must be low prior to en-

tering the preload/observe state, and low prior to leaving the pre-

load/observe state. Pin 1 must be low prior to entering the pre-

load/observe state.

Preload / Observe Register Scan Order

Quadrant

Pin

Quadrant 1

Pin

4

5

6

•••

15

17

Q2

Q1

B23

Q2

Q1

Q2

Q1

•••

B18

Q2

Q1

Q2

Q1

(Quadrant 2)

Quadrant 2

Pin

18

19

21

22

•••

31

(Quadrant 1)

→

Q2

Q1

Q2

Q1

B17

Q2

Q1

Q2

Q1

•••

B12

Q2

Q1

(Quadrant 3)

Quadrant 3

Pin

38

39

40

•••

49

51

(Quadrant 2)

→

Q2

Q1

B11

Q2

Q1

Q2

Q1

•••

B6

Q2

Q1

Q2

Q1

(Quadrant 4)

Quadrant 4

Pin

52

53

55

56

•••

65

(Quadrant 3)

→

Q2

Q1

Q2

Q1

B5

Q2

Q1

Q2

Q1

•••

B0

Q2

Q1

CLOCK

VH

PRELOAD

tD

tHP

tD

tSP

DATA IN

tEAP

tERP

OE

DATA OUT

tCOP

tPR

Pin 65

New Q1

Pin 65

New Q2

Pin

65

Q1

Clock

#1

Clock

#2

Clock

#128

Pin

65

Q2

Pin

4

Q2

Pin

65

Q1

tWPP

tWPP

1-200

ATV5000/L