CPC5601

12

www.clare.com

R3.0

3. Programming

3.1 Latch Circuit Description

Data applied to the input pin is optically coupled to the

shift register through a pulse generator. Each low-to-

high transition in the pulse generator triggers a clock

pulse. Clock pulses are applied to the CLK input of six

rising-edge-triggered flip-flops. The non-inverted input

data is fed to the flip-flops at all times, but the flip-flops

are only clocked on receipt of a pulse from the pulse

generator. The flip-flops drive six FET switches.

3.2 Programming Protocol

Figure 6. Latch Circuit Timing to Turn an Output On

A setup pulse on the input of at least 50

µS starts the

bit programming sequence. The trailing edge of the

setup pulse starts a timer on the CPC5601 (t0). After

140

µS, the value of the input is latched into the shift

register.

To set an output, hold the input high for 200

µS from

the leading edge after the setup pulse. This turns on

the corresponding open-drain FET to sink current.

Figure 7. Latch Circuit Timing to Turn an Output Off

To clear an output, hold the input high for 50

µS after

the setup pulse, then take the input low for at least 150

µS.

Repeat the sequence of the setup pulse followed by

the appropriate input condition for each successive bit.

Bear the following in mind while programming the

CPC5601:

INPUT (pin 3)

CLOCK

B1 (pin 13)

140 s

µ

200 s

µ

B1 output FET on (sinking current)

B1 output FET off (drain open)

t0

>=50 s (tsetup)

µ

thold

Transition after setup time

initiates clock pulse

First flip-flop reads data

at the rising edge of the clock

B1 output FET off (drain open)

Transition after setup time

initiates clock pulse

First flip-flop reads data

at the rising edge of the clock

INPUT (pin 3)

CLOCK

B1 (pin 13)

140 s

m

B1 output FET on (sinking current)

t0

50 s

m

>=50 s (tsetup)

m

150 s min

m