CX25871 datasheet(19/291 Pages) CONEXANT

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CX25870/871

1.0 Functional Description

Flicker-Free Video Encoder with Ultrascale Technology

1.1 Pin Descriptions

100381B

Conexant

1-3

VDD_CO

—

Clock output supply pin. This pin should be tied to the power supply. For low

voltage infacing this pin should be tied to the low voltage supply.

CLKO

Pixel clock output (TTL compatible). This pin is three-state if the CLKI pin

provides the encoder clock.

VSS_CO

—

Clock output ground pin. This pin should be tied to the ground plane.

CLKI

Pixel clock input (TTL compatible). This may be used as either the encoder

clock or a delayed version of the CLKO pin synchronized with the pixel data

input.

RESET*

Reset control input (TTL compatible). A logical 0 applied for a minimum of 20

CLKI clock cycles resets and disables video timing (horizontal, vertical,

subcarrier counters) to the start of VSYNC of the first field and resets the serial

interface registers. RESET* must be a logical 1(3.3 V) for normal operation.

SLEEP

Power-down control input (TTL compatible). A logical 1 configures the device

for power-down mode. A logical 0 configures the device for normal operation.

SLAVE

Slave/master mode select input (TTL compatible). A logical 1 configures the

device for slave video timing operation. A logical 0 configures the device for

master video timing operation.

PAL

PAL/NTSC mode select input (TTL compatible). A logical 1 configures the

device for PAL video format and Autoconfiguration Mode 1. A logical 0

configures the device for NTSC video format and Autoconfiguration Mode 0.

VDD_VREF

Input threshold adjustment. This pin should be tied to VDD for 3.3 V input

swings or VDDL/2 for low voltage input swings.

ALTADDR

Alternate slave address input (TTL compatible). A logical 0 configures the

device to respond to a serial write address of 0x88. A logical 1 configures the

device to respond to a serial write address of 0x8A. In addition, serial reads to

address 0x89 (ALTADDR = 0) or 0x8B (ALTADDR = 1) are possible with this pin.

VDD_SI

—

Serial interface input supply pin. This pin should be tied to VDD (3.3 V).

VDD_SO

—

Serial interface output supply pin. This pin should be tied to VDD (3.3 V).

SIC

Serial interface clock input (TTL compatible).

SID

I/O

Serial interface data input/output (TTL compatible). Data is written to and read

from the device via this serial bus.

VSS_SO

—

Serial interface input ground pin. This pin should be tied to the ground plane.

VSS_SI

—

Serial interface input ground pin. This pin should be tied to the ground plane.

VDDL

—

Digital power for low voltage interface. All VAA and VDD pins must be

connected together on the same PCB plane to prevent latchup. For a low voltage

interface, this pin should be tied to the low voltage supply.

VSS/TEST

Test pin. Should be tied to VSS for normal operation.

BLANK*

I/O

Composite blanking control (TTL compatible). This can be generated by the

encoder or supplied from the graphics controller. If internal blanking is used,

this pin can be used to indicate the control character clock edge. If unused,

BLANK* should be tied high through a 10 k

Ω pullup resistor.

Table 1-1. Pin Assignments (2 of 3)

Pin Name

I/O

Pin #

Description

CX25871 Datasheet(PDF) 19 Page - Synaptics Incorporated.

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