Philips Semiconductors

Product specification

74F598

8-bit shift register with input storage registers (3-State)

2

1991 Oct 21

853–1583 04407

FEATURES

• High impedance PNP base input for reduced loading (20µA in

High and Low states)

• 8–bit parallel storage register

• Shift register has asynchronous direct overriding reset

• Shift load SHLD is functional when SHCP is Low and locked out

when SHCP is High.

• Guaranteed shift frequency DC to 105MHz

• Parallel 3–State I/O storage register inputs and shift register

parallel outputs

DESCRIPTION

The 74F598 consists of an 8–bit storage register feeding a

parallel–in/serial–in, parallel–out/serial–out 8–bit shift register. Both

the storage register and shift register have positive edge–triggered

clocks. The shift register has asynchronous reset and when SHCP

is Low, it has asynchronous load.

The shift register load function has been modified to load when both

SHLD and SHCP are Low. When SHCP is High the shift register

load operation is not performed. Data will be properly shifted on the

rising edge of SHCP when SHLD is High.

TYPE

TYPICAL SUPPLY

CURRENT (TOTAL)

74F598

100MHz

75mA

ORDERING INFORMATION

ORDER CODE

DESCRIPTION

COMMERCIAL RANGE

PKG DWG #

20–pin plastic DIP

N74F598N

SOT146-1

20–pin plastic SOL

N74F598D

SOT163-1

INPUT AND OUTPUT LOADING AND FAN OUT TABLE

PINS

DESCRIPTION

74F (U.L.) High/

Low

LOAD VALUE

High/Low

I/On

Parallel data input

1.0/0.033

20

µA/20µA

Ds0, Ds1

Serial data inputs

1.0/0.033

20

µA/20µA

SHCP

Shift register clock pulse input

1.0/0.033

20

µA/20µA

STCP

Storage register clock pulse input

1.0/0.033

20

µA/20µA

SHCPEN

Shift register clock pulse enable input

1.0/0.033

20

µA/20µA

SHLD

Shift register load input (active Low)

1.0/0.033

20

µA/20µA

SHRST

Shift register reset input (active Low)

1.0/0.033

20

µA/20µA

S

Serial data select input

1.0/0.033

20

µA/20µA

OE

Output enable input

1.0/0.033

20

µA/20µA

Qs

Serial data output

50/33

1.0mA/20mA

I/On

Parallel data outputs

150/40

3.0mA/24mA

Note to input and output loading and fan out table

1. One (1.0) FAST unit load is defined as: 20

µA in the High state and 0.6mA in the Low state.

PIN CONFIGURATION

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20 VCC

S

DS0

DS1

OE

STCP

SHCPEN

SHCP

SHRST

Qs

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

SHLD

GND

SF00375

LOGIC SYMBOL

Qs

GND = Pin 10

S

OE

STCP

SHCPEN

SHCP

SHRST

SHLD

19

16

15

14

13

12

9

11

Ds0

18

Ds1

17

I/O0

1

I/O1

2

I/O2

3

I/O3

4

I/O4

5

I/O5

6

I/O6

7

I/O7

8

SF00376