PIC16F15213 datasheet(170/439 Pages) MICROCHIP

170 / 439 page

Figure 20-7. Timer1 Gate Single Pulse and Toggle Combined Mode

TxG_IN

TxGGO/

DONE

TxGSPM

TxGPOL

TMRxGE

Set by software

Counting enabled on

rising edge of TxG

Cleared by hardware on

falling edge of TxGVAL

TxGTM

TMRxGIF

Cleared by software

Cleared by

software

Set by hardware on

falling edge of TxGVAL

TIMER1

TxGVAL

TxCKI

20.6.5

Timer1 Gate Value Status

When Timer1 gate value status is utilized, it is possible to read the most current level of the gate control value. The

value is stored in the GVAL bit in the TxGCON register. The GVAL bit is valid even when the Timer1 gate is not

enabled (GE bit is cleared).

20.6.6

Timer1 Gate Event Interrupt

When Timer1 gate event interrupt is enabled, it is possible to generate an interrupt upon the completion of a

gate event. When the falling edge of GVAL occurs, the TMRxGIF flag bit will be set. If the TMRxGIE bit in the

corresponding PIE register is set, then an interrupt will be recognized.

The TMRxGIF flag bit operates even when the Timer1 gate is not enabled (GE bit is cleared).

20.7

Timer1 Interrupt

The TMRx register increments to FFFFh and rolls over to 0000h. When TMRx rolls over, the TMRx Interrupt Flag

(TMRxIF) bit of the PIRx register is set. To enable the interrupt-on-rollover, the following bits must be set:

• ON bit of the TxCON register

• TMRxIE bits of the PIEx register

• Global interrupts must be enabled

The interrupt is cleared by clearing the TMRxIF bit as a task in the Interrupt Service Routine.

PIC16F15213/14/23/24/43/44

TMR1 - Timer1 Module with Gate Control

and its subsidiaries

Data Sheet

DS40002195E-page 170

PIC16F15213 Datasheet(PDF) 170 Page - Microchip Technology

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